FEATURES■■■■■■■■■■■■■■■LTC2444/LTC2445/LTC2448/LTC244924-Bit High Speed8-/16-Channel ∆Σ ADCs withSelectable Speed/ResolutionDESCRIPTIOThe LTC®2444/LTC2445/LTC2448/LTC2449 are 8-/16-channel (4-/8-differential) high speed 24-bit No Latency∆ΣTM ADCs. They use a proprietary delta-sigma architec-ture enabling variable speed/resolution. Through a simple4-wire serial interface, ten speed/resolution combinations6.9Hz/280nVRMS to 3.5kHz/25µVRMS (4kHz with externaloscillator) can be selected with no latency between con-version results or shift in DC accuracy (offset, full-scale,linearity, drift). Additionally, a 2X speed mode can beselected enabling output rates up to 7kHz (8kHz if anexternal oscillator is used) with one cycle latency.Any combination of single-ended or differential inputs canbe selected with a common mode input range from groundto VCC, independent of VREF. While operating in the 1Xspeed mode the first conversion following a new speed,resolution, or channel selection is valid. Since there is nosettling time between conversions, all 8 differential chan-nels can be scanned at a rate of 500Hz. At the conclusionof each conversion, the converter is internally reset elimi-nating any memory effects between successive conver-sions and assuring stability of the high order delta-sigmamodulator., LTC and LT are registered trademarks of Linear Technology Corporation.No Latency ∆Σ is a trademark of Linear Technology Corporation.UAPPLICATIO S■■■■■Up to 8 Differential or 16 Single-Ended InputChannelsUp to 8kHz Output RateUp to 4kHz Multiplexing RateSelectable Speed/Resolution2µVRMS Noise at 1.76kHz Output Rate200nVRMS Noise at 13.8Hz Output Rate withSimultaneous 50/60Hz RejectionGuaranteed Modulator Stability and Lock-UpImmunity for any Input and Reference Conditions0.0005% INL, No Missing CodesAutosleep Enables 20µA Operation at 6.9Hz<5µV Offset (4.5V < VCC < 5.5V, –40°C to 85°C)Differential Input and Differential Reference withGND to VCC Common Mode RangeNo Latency Mode, Each Conversion is Accurate EvenAfter a New Channel is SelectedInternal Oscillator—No External ComponentsLTC2445/LTC2449 Include MUXOUT/ADCIN forExternal Buffering or GainTiny QFN 5mm x 7mm PackageHigh Speed MultiplexingWeight ScalesAuto Ranging 6-Digit DVMsDirect Temperature MeasurementHigh Speed Data AcquisitionTYPICAL APPLICATIOSimple 24-Bit Variable Speed Data Acquisition System4.5V TO 5.5V1µFCH0CH1•••CH7CH8•••CH15COMREF–GNDLTC24482444 TA01REF+VCCFOSDISCKSDOCSRMS NOISE (µV)= EXTERNAL OSCILLATOR= INTERNAL OSCILLATOR (SIMULTANEOUS 50Hz/60Hz REJECTION AT 6.9Hz OUTPUT RATE)4-WIRESPI INTERFACETHERMOCOUPLE16-CHANNELMUX+–VARIABLE SPEED/RESOLUTIONDIFFERENTIAL24-BIT ∆Σ ADCUU1001010.11LTC2444/LTC2448Speed vs RMS NoiseVCC = 5VVREF = 5VVIN+ = VIN– = 0V2X SPEED MODENO LATENCY MODE2.8µV AT 880Hz280nV AT 6.9Hz(50/60Hz REJECTION)100010100CONVERSION RATE (Hz)100002440 TA02 sn2444589 2444589fs1
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LTC2444/LTC2445/LTC2448/LTC2449ABSOLUTE AXIU RATIGS(Notes 1, 2)Supply Voltage (VCC) to GND.......................–0.3V to 6VAnalog Input Pins Voltage to GND....................................–0.3V to (VCC + 0.3V)Reference Input Pins Voltage to GND....................................–0.3V to (VCC + 0.3V)Digital Input Voltage to GND........–0.3V to (VCC + 0.3V)Digital Output Voltage to GND.....–0.3V to (VCC + 0.3V)WUPACKAGE/ORDER IFORATIOTOP VIEWGNDGNDSDOSCKSDICSFOUGND38373635343332GND1BUSY2EXT3GND4GND5GND6COM7NC8CH09CH110NC11NC1213141516171819NCNCCH2CH3CH4CH5NC31GND30REF–29REF+28VCC27NC26NC25NC24NC23NC22CH721CH620NCLTC2444CUHFLTC2444IUHF38373635343332GND1BUSY2EXT3GND4GND5GND6COM7NC8CH09CH110NC11NC12
13141516171819
NCNCCH2CH3CH4CH5NC31GND30REF–29REF+28VCC27MUXOUTN26ADCINN25ADCINP24MUXOUTP23NC22CH721CH620NC
GNDSDOSCKSDICSFOORDER PARTNUMBERQFN PART MARKING*2444UHF PACKAGE38-LEAD (5mm × 7mm) PLASTIC QFNTJMAX = 125°C, θJA = 34°C/WTOP VIEWGNDGNDSDOSCKSDICSFO38373635343332GND1BUSY2EXT3GND4GND5GND6COM7CH08CH19CH210CH311CH41213141516171819CH5CH6CH7CH8CH9CH10CH1131GND30REF–29REF+28VCC27NC26NC25NC24NC23CH1522CH1421CH1320CH12ORDER PARTNUMBERLTC2448CUHFLTC2448IUHFGND38373635343332GND1BUSY2EXT3GND4GND5GND6COM7CH08CH19CH210CH311CH4121314151617181931GND30REF28VCC27MUXOUTN26ADCINN25ADCINP24MUXOUTP23CH1522CH1421CH1320CH12–GNDSDOSCKSDICSFOQFN PART MARKING*2448CH5CH6CH7CH8CH9CH10UHF PACKAGE38-LEAD (5mm × 7mm) PLASTIC QFNUHF PACKAGE38-LEAD (5mm × 7mm) PLASTIC QFNTJMAX = 125°C, θJA = 34°C/WTJMAX = 125°C, θJA = 34°C/W*The temperature grade is identified by a label on the shipping container. Consult LTC Marketing for parts specified with wider operating temperature ranges. sn2444589 2444589fs
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CH11UWWWOperating Temperature RangeLTC2444C/LTC2445C/LTC2448C/LTC2449C..............................0°C to 70°CLTC2444I/LTC2445I/LTC2448I/LTC2449I...........................–40°C to 85°CStorage Temperature Range.................–65°C to 125°CTOP VIEW
ORDER PARTNUMBERLTC2445CUHFLTC2445IUHFQFN PART MARKING*2445UHF PACKAGE
38-LEAD (5mm × 7mm) PLASTIC QFN
TJMAX = 125°C, θJA = 34°C/WTOP VIEWORDER PARTNUMBERLTC2449CUHFLTC2449IUHF29REF+QFN PART MARKING*2449元器件交易网www.cecb2b.com
LTC2444/LTC2445/LTC2448/LTC2449The ● denotes specifications which apply over the full operatingtemperature range, otherwise specifications are at TA = 25°C. (Notes 3, 4)PARAMETERResolution (No Missing Codes)Integral NonlinearityOffset ErrorOffset Error DriftPositive Full-Scale ErrorPositive Full-Scale Error DriftNegative Full-Scale ErrorNegative Full-Scale Error DriftTotal Unadjusted ErrorCONDITIONS0.1V ≤ VREF ≤ VCC, –0.5 • VREF ≤ VIN ≤ 0.5 • VREF, (Note 5)VCC = 5V, REF+ = 5V, REF– = GND, VINCM = 2.5V, (Note 6)REF+ = 2.5V, REF– = GND, VINCM = 1.25V, (Note 6)2.5V ≤ REF+ ≤ VCC, REF– = GND,GND ≤ IN+ = IN– ≤ VCC (Note 12)2.5V ≤ REF+ ≤ VCC, REF– = GND,GND ≤ IN+ = IN– ≤ VCCREF+ = 5V, REF– = GND, IN+ = 3.75V, IN– = 1.25VREF+ = 2.5V, REF– = GND, IN+ = 1.875V, IN– = 0.625V2.5V ≤ REF+ ≤ VCC, REF– = GND,IN+ = 0.75REF+, IN– = 0.25 • REF+REF+ = 5V, REF– = GND, IN+ = 1.25V, IN– = 3.75VREF+ = 2.5V, REF– = GND, IN+ = 0.625V, IN– = 1.875V2.5V ≤ REF+ ≤ VCC, REF– = GND,IN+ = 0.25 • REF+, IN– = 0.75 • REF+5V ≤ VCC ≤ 5.5V, REF+ = 2.5V, REF– = GND, VINCM = 1.25V5V ≤ VCC ≤ 5.5V, REF+ = 5V, REF– = GND, VINCM = 2.5VREF+ = 2.5V, REF– = GND, VINCM = 1.25V, (Note 6)2.5V ≤ REF+ ≤ VCC, REF– = GND,GND ≤ IN– = IN+ ≤ VCC●●●●●●●ELECTRICAL CHARACTERISTICSMIN24TYP532.52010100.210100.2151515120MAX155UNITSBitsppm of VREFppm of VREFµVnV/°C5050ppm of VREFppm of VREFppm of VREF/°C5050ppm of VREFppm of VREFppm of VREF/°Cppm of VREFppm of VREFppm of VREFdBInput Common Mode Rejection DCUUAALOG IPUT AD REFERECEThe ● denotes specifications which apply over the full operatingtemperature range, otherwise specifications are at TA = 25°C. (Note 3)PARAMETERAbsolute/Common Mode IN+ VoltageAbsolute/Common Mode IN– VoltageInput Differential Voltage Range(IN+ – IN–)Absolute/Common Mode REF+ VoltageAbsolute/Common Mode REF– VoltageReference Differential Voltage Range(REF+ – REF–)IN+ Sampling CapacitanceIN– Sampling CapacitanceREF+ Sampling CapacitanceREF– Sampling CapacitanceLeakage Current, Inputs and ReferenceAverage Input/Reference CurrentDuring SamplingMUX Break-Before-MakeMUX Off IsolationVIN = 2VP-P DC to 1.8MHzCS = VCC, IN+ = GND, IN– = GND,REF+ = 5V, REF– = GND●UUSYMBOLIN+IN–VINREF+REF–VREFCS(IN+)CS(IN–)CS(REF+)CS(REF–)IDC_LEAK(IN+, IN–, REF+, REF–)CONDITIONS●●●●●●MINGND – 0.3VGND – 0.3V–VREF/20.1GND0.1TYPMAXVCC + 0.3VVCC + 0.3VVREF/2VCCVCC – 0.1VVCCUNITSVVVVVVpFpFpFpF2222–15115nAnAnsdBISAMPLE(IN+, IN–, REF+, REF–)Varies, See Applications Section50120tOPENQIRR sn2444589 2444589fs
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LTC2444/LTC2445/LTC2448/LTC2449DIGITAL IPUTS AD DIGITAL OUTPUTSSYMBOLVIHVILVIHVILIINIINCINCINVOHVOLVOHVOLIOZPARAMETERHigh Level Input VoltageCS, FOLow Level Input VoltageCS, FOHigh Level Input VoltageSCKLow Level Input VoltageSCKDigital Input CurrentCS, FO, EXT, SOIDigital Input CurrentSCKDigital Input CapacitanceCS, FODigital Input CapacitanceSCKHigh Level Output VoltageSDO, BUSYLow Level Output VoltageSDO, BUSYHigh Level Output VoltageSCKLow Level Output VoltageSCKHi-Z Output LeakageSDO(Note 8)IO = –800µAIO = 1.6mAIO = –800µA (Note 9)IO = 1.6mA (Note 9)●●●●●The ● denotes specifications which apply over the fulloperating temperature range, otherwise specifications are at TA = 25°C. (Note 3)CONDITIONS4.5V ≤ VCC ≤ 5.5V4.5V ≤ VCC ≤ 5.5V4.5V ≤ VCC ≤ 5.5V (Note 8)4.5V ≤ VCC ≤ 5.5V (Note 8)0V ≤ VIN ≤ VCC0V ≤ VIN ≤ VCC (Note 8)●●●●●●POWER REQUIRE E TSSYMBOLVCCICCPARAMETERSupply VoltageSupply CurrentConversion ModeSleep ModeThe ● denotes specifications which apply over the full operating temperature range,otherwise specifications are at TA = 25°C. (Note 3)CONDITIONS●WUTI I G CHARACTERISTICSSYMBOLfEOSCtHEOtLEOtCONVPARAMETERExternal Oscillator Frequency RangeExternal Oscillator High PeriodExternal Oscillator Low PeriodConversion TimeThe ● denotes specifications which apply over the full operating temperaturerange, otherwise specifications are at TA = 25°C. (Note 3)CONDITIONS●●●fISCKInternal SCK Frequency4
UWUUMIN2.5TYPMAXUNITSV0.82.50.8–10–101010VCC – 0.5V0.4VVCC – 0.5V0.4V–10101010VVVµAµApFpFVVVVµAMIN4.5TYPMAX5.5UNITSVmAµACS = 0V (Note 7)CS = VCC (Note 7)●●881130MIN0.125250.99126TYPMAX201000010000UNITSMHznsnsmsmsmsOSR = 256 (SDI = 0)OSR = 32768 (SDI = 1)External Oscillator (Notes 10, 13)Internal Oscillator (Note 9)External Oscillator (Notes 9, 10)●●●●1.1314540 • OSR +170fEOSC (kHz)1.331700.80.9fEOSC/101MHzHz sn2444589 2444589fs
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LTC2444/LTC2445/LTC2448/LTC2449TIIG CHARACTERISTICSSYMBOLDISCKfESCKtLESCKtHESCKtDOUT_ISCKtDOUT_ESCKt1t2t3t4tKQMAXtKQMINt5t6t7t8PARAMETERInternal SCK Duty CycleExternal SCK Frequency RangeExternal SCK Low PeriodExternal SCK High PeriodInternal SCK 32-Bit Data Output TimeExternal SCK 32-Bit Data Output TimeCS ↓ to SDO Low ZCS ↑ to SDO High ZCS ↓ to SCK ↓CS ↓ to SCK ↑SCK ↓ to SDO ValidSDO Hold After SCK ↓SCK Set-Up Before CS ↓SCK Hold After CS ↓SDI Setup Before SCK ↑SDI Hold After SCK ↑The ● denotes specifications which apply over the full operating temperaturerange, otherwise specifications are at TA = 25°C. (Note 3)CONDITIONS(Note 9)(Note 8)(Note 8)(Note 8)Internal Oscillator (Notes 9, 11)External Oscillator (Notes 9, 10)(Note 8)(Note 12)(Note 12)(Note 9)(Notes 8, 12)(Note 5)●●●●●●●●●●●●●●Note 1: Absolute Maximum Ratings are those values beyond which the lifeof the device may be impaired.Note 2: All voltage values are with respect to GND.Note 3: VCC = 4.5V to 5.5V unless otherwise specified.VREF = REF+ – REF–, VREFCM = (REF+ + REF–)/2;VIN = IN+ – IN–, VINCM = (IN+ + IN–)/2.Note 4: FO pin tied to GND or to external conversion clock source withfEOSC = 10MHz unless otherwise specified.Note 5: Guaranteed by design, not subject to test.Note 6: Integral nonlinearity is defined as the deviation of a code from astraight line passing through the actual endpoints of the transfer curve.The deviation is measured from the center of the quantization band.PI FU CTIO SGND (Pins 1, 4, 5, 6, 31, 32, 33): Ground. Multipleground pins internally connected for optimum groundcurrent flow and VCC decoupling. Connect each one ofthese pins to a common ground plane through a lowimpedance connection. All 7 pins must be connected toground for proper operation.BUSY (Pin 2): Conversion in Progress Indicator. This pinis HIGH while the conversion is in progress and goes LOWindicating the conversion is complete and data is ready. Itremains LOW during the sleep and data output states. Atthe conclusion of the data output state, it goes HIGHindicating a new conversion has begun.EXT (Pin 3): Internal/External SCK Selection Pin. This pinis used to select internal or external SCK for outputting/inputting data. If EXT is tied low, the device is in theexternal SCK mode and data is shifted out of the deviceunder the control of a user applied serial clock. If EXT istied high, the internal serial clock mode is selected. Thedevice generates its own SCK signal and outputs this onthe SCK pin. A framing signal BUSY (Pin 2) goes lowindicating data is being output.COM (Pin 7): The common negative input (IN–) for allsingle ended multiplexer configurations. The voltage onCH0-CH15 and COM pins can have any value between sn2444589 2444589fs
UUUWMIN45252541.6TYPMAX5520UNITS%MHznsns35.3320/fEOSC32/fESCK30.9µsssnsnsµsns005252525251550501010nsnsnsnsnsns(Note 5)(Note 5)●●Note 7: The converter uses the internal oscillator.Note 8: The converter is in external SCK mode of operation such that theSCK pin is used as a digital input. The frequency of the clock signal drivingSCK during the data output is fESCK and is expressed in Hz.Note 9: The converter is in internal SCK mode of operation such that theSCK pin is used as a digital output. In this mode of operation, the SCK pinhas a total equivalent load capacitance of CLOAD = 20pF.Note 10: The external oscillator is connected to the FO pin. The externaloscillator frequency, fEOSC, is expressed in Hz.Note 11: The converter uses the internal oscillator. FO = 0V.Note 12: Guaranteed by design and test correlation.Note 13: There is an internal reset that adds an additional 1µs (typ) to theconversion time.U5
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LTC2444/LTC2445/LTC2448/LTC2449PI FUCTIOSGND – 0.3V to VCC + 0.3V. Within these limits, the twoselected inputs (IN+ and IN–) provide a bipolar input range(VIN = IN+ – IN–) from –0.5 • VREF to 0.5 • VREF. Outside thisinput range, the converter produces unique over-rangeand under-range output codes.CH0 to CH15 (Pins 8-23): LTC2448/LTC2449 AnalogInputs. May be programmed for single-ended or differen-tial mode.CH0 to CH7 (Pins 9, 10, 13, 14, 17, 18, 21, 22): LTC2444/LTC2445 Analog Inputs. May be programmed for single-ended or differential mode.NC (Pins 8, 11, 12, 15, 16, 19, 20, 23): LTC2444/LTC2445 No Connect/Channel Isolation Shield. May beleft floating or tied to any voltage 0 to VCC in order toprovide isolation for pairs of differential input channels.NC (Pins 24, 25, 26, 27): LTC2444/LTC2448 No Connect.These pins can either be tied to ground or left floating.MUXOUTP (Pin 24): LTC2445/LTC2449 Positive Multi-plexer Output. Used to drive the input to an external buffer/amplifier.ADCINP (Pin 25): LTC2445/LTC2449 Positive ADC Input.Tie to output of buffer/amplifier driven by MUXOUTP.ADCINN (Pin 26): LTC2445/LTC2449 Negative ADC Input.Tie to output of buffer/amplifier driven by MUXOUTN.MUXOUTN (Pin 27): LTC2445/LTC2449 Negative Multi-plexer Output. Used to drive the input to an external buffer/amplifier.VCC (Pin 28): Positive Supply Voltage. Bypass to GND witha 10µF tantalum capacitor in parallel with a 0.1µF ceramiccapacitor as close to the part as possible.REF+ (Pin 29), REF– (Pin 30): Differential ReferenceInput. The voltage on these pins can have any valuebetween GND and VCC as long as the reference positiveinput, REF+, is maintained more positive than the negativereference input, REF+, by at least 0.1V.SDI (Pin 34): Serial Data Input. This pin is used to selectthe speed, 1X or 2X mode, resolution, and input channel,for the next conversion cycle. At initial power up, thedefault mode of operation is CH0-CH1, OSR of 256, and 1Xmode. The serial data input contains an enable bit whichdetermines if a new channel/speed is selected. If this bit islow the following conversion remains at the same speedand selected channel. The serial data input is applied to thedevice under control of the serial clock (SCK) during thedata output cycle. The first conversion following a newchannel/speed is valid.FO (Pin 35): Frequency Control Pin. Digital input thatcontrols the internal conversion clock. When FO is con-nected to VCC or GND, the converter uses its internaloscillator running at 9MHz. The conversion rate is deter-mined by the selected OSR such that tCONV (ms) = 40 •OSR + 170/fOSC (kHz). The first digital filter null is locatedat 8/tCONV, 7kHz at OSR = 256 and 55Hz (Simultaneous 50/60Hz) at OSR = 32768. This pin may be driven with amaximum external clock of 10.24MHz resulting in a maxi-mum 8kHz output rate (OSR = 64, 2X Mode).CS (Pin 36): Active Low Chip Select. A LOW on this pinenables the SDO ditital output and wakes up the ADC.Following each conversion the ADC automatically entersthe sleep mode and remains in this low power state as longas CS is HIGH. A LOW-to-HIGH transition on CS during theData Output aborts the data transfer and starts a newconversion.SDO (Pin 37): Three-State Digital Output. During the dataoutput period, this pin is used as serial data output. Whenthe chip select CS is HIGH (CS = VCC) the SDO pin is in ahigh impedance state. During the conversion and sleepperiods, this pin is used as the conversion status output.The conversion status can be observed by pulling CSLOW. This signal is HIGH while the conversion is inprogress and goes LOW once the conversion is complete.SCK (Pin 38): Bidirectional Digital Clock Pin. In internalserial clock operation mode, SCK is used as a digital outputfor the internal serial interface clock during the data outputperiod. In the external serial clock operation mode, SCK isused as the digital input for the external serial interfaceclock during the data output period. The serial clockoperation mode is determined by the logic level applied tothe EXT pin. sn2444589 2444589fs
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LTC2444/LTC2445/LTC2448/LTC2449WFUCTIOAL BLOCK DIAGRA GNDREF+REF–CH0CH1IN+•••MUXIN–TEST CIRCUITS SDO1.69kCLOAD = 20pFSDOAPPLICATIOS IFORATIOCONVERTER OPERATIONConverter Operation CycleThe LTC2444/LTC2445/LTC2448/LTC2449 are multi-channel, high speed, delta-sigma analog-to-digital con-verters with an easy to use 3- or 4-wire serial interface (seeFigure 1). Their operation is made up of three states. Theconverter operating cycle begins with the conversion,followed by the low power sleep state and ends with thedata output/input (see Figure 2). The 4-wire interfaceconsists of serial data input (SDI), serial data output(SDO), serial clock (SCK) and chip select (CS). The inter-face, timing, operation cycle and data out format is com-patible with Linear’s entire family of ∆Σ converters.UWUUUUVCCAUTOCALIBRATIONAND CONTROLINTERNALOSCILLATORFO(INT/EXT)–+SERIALINTERFACEDECIMATING FIRADDRESS2444 F01CH15COMDIFFERENTIAL3RD ORDER∆Σ MODULATORSDISCKSDOCSFigure 1. Functional Block DiagramVCC1.69kCLOAD = 20pFHi-Z TO VOHVOL TO VOHVOH TO Hi-Z2440 TA03Hi-Z TO VOLVOH TO VOLVOL TO Hi-Z2440 TA04POWER UPIN+=CH0, IN–=CH1OSR=256,1X MODECONVERTSLEEP CS = LOW ANDSCK CHANNEL SELECTSPEED SELECTDATA OUTPUT2444 F02Figure 2. LTC2444/LTC2445/LTC2448/LTC2449State Transition Diagram sn2444589 2444589fs7
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LTC2444/LTC2445/LTC2448/LTC2449APPLICATIOS IFORATIOInitially, the LTC2444/LTC2445/LTC2448/LTC2449 per-form a conversion. Once the conversion is complete, thedevice enters the sleep state. While in this sleep state,power consumption is reduced below 10µA. The partremains in the sleep state as long as CS is HIGH. Theconversion result is held indefinitely in a static shiftregister while the converter is in the sleep state.Once CS is pulled LOW, the device begins outputting theconversion result. There is no latency in the conversionresult while operating in the 1x mode. The data output cor-responds to the conversion just performed. This result isshifted out on the serial data out pin (SDO) under the con-trol of the serial clock (SCK). Data is updated on the fallingedge of SCK allowing the user to reliably latch data on therising edge of SCK (see Figure 3). The data output state isconcluded once 32 bits are read out of the ADC or when CSis brought HIGH. The device automatically initiates a newconversion and the cycle repeats.Through timing control of the CS, SCK and EXT pins, theLTC2444/LTC2445/LTC2448/LTC2449 offer several flex-ible modes of operation (internal or external SCK). Thesevarious modes do not require programming configurationregisters; moreover, they do not disturb the cyclic opera-tion described above. These modes of operation aredescribed in detail in the Serial Interface Timing Modessection.Ease of UseThe LTC2444/LTC2445/LTC2448/LTC2449 data outputhas no latency, filter settling delay or redundant dataassociated with the conversion cycle while operating inthe 1X mode. There is a one-to-one correspondencebetween the conversion and the output data. Therefore,multiplexing multiple analog voltages is easy. Speed/resolution adjustments may be made seamlessly be-tween two conversions without settling errors.The LTC2444/LTC2445/LTC2448/LTC2449 perform off-set and full-scale calibrations every conversion cycle. Thiscalibration is transparent to the user and has no effect onthe cyclic operation described above. The advantage ofcontinuous calibration is extreme stability of offset andfull-scale readings with respect to time, supply voltagechange and temperature drift.8
UPower-Up SequenceThe LTC2444/LTC2445/LTC2448/LTC2449 automaticallyenter an internal reset state when the power supplyvoltage VCC drops below approximately 2.2V. This fea-ture guarantees the integrity of the conversion result andof the serial interface mode selection.When the VCC voltage rises above this critical threshold,the converter creates an internal power-on-reset (POR)signal with a duration of approximately 0.5ms. The PORsignal clears all internal registers. The conversion imme-diately following a POR is performed on the input channelIN+ = CH0, IN– = CH1 at an OSR = 256 in the 1X mode.Following the POR signal, the LTC2444/LTC2445/LTC2448/LTC2449 start a normal conversion cycle and follow thesuccession of states described above. The first conver-sion result following POR is accurate within the specifica-tions of the device if the power supply voltage is restoredwithin the operating range (4.5V to 5.5V) before the end ofthe POR time interval.Reference Voltage RangeThese converters accept a truly differential external refer-ence voltage. The absolute/common mode voltage speci-fication for the REF+ and REF– pins covers the entire rangefrom GND to VCC. For correct converter operation, theREF+ pin must always be more positive than the REF– pin.The LTC2444/LTC2445/LTC2448/LTC2449 can accept adifferential reference voltage from 0.1V to VCC. The con-verter output noise is determined by the thermal noise ofthe front-end circuits, and as such, its value in microvoltsis nearly constant with reference voltage. A decrease inreference voltage will not significantly improve theconverter’s effective resolution. On the other hand, areduced reference voltage will improve the converter’soverall INL performance.Input Voltage RangeThe analog input is truly differential with an absolute/common mode range for the CH0-CH15 and COM inputpins extending from GND – 0.3V to VCC + 0.3V. Outsidethese limits, the ESD protection devices begin to turn onand the errors due to input leakage current increaserapidly. Within these limits, the LTC2444/LTC2445/ sn2444589 2444589fs
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LTC2444/LTC2445/LTC2448/LTC2449APPLICATIOS IFORATIOLTC2448/LTC2449 convert the bipolar differential inputsignal, VIN = IN+ – IN– (where IN+ and IN– are the selectedinput channels), from –FS = –0.5 • VREF to +FS = 0.5 • VREFwhere VREF = REF+ – REF–. Outside this range, the con-verter indicates the overrange or the underrange conditionusing distinct output codes.MUXOUT/ADCINThere are two differences between the LTC2444/LTC2448and the LTC2445/LTC2449. The first is the RMS noiseperformance. For a given OSR, the LTC2445/LTC2449noise level is approximately √2 times lower (0.5 effectivebits)than that of the LTC2444/LTC2448.The second difference is the LTC2445/LTC2449 includesMUXOUT/ADCIN pins. These pins enable an external bufferor gain block to be inserted between the output of themultiplexer and the input to the ADC. Since the buffer isdriven by the output of the multiplexer, only one circuit isrequired for all 16 input channels. Additionally, the trans-parent calibration feature of the LTC244X family automati-cally removes the offset errors of the external buffer.In order to achieve optimum performance, the MUXOUTand ADCIN pins should not be shorted together. In appli-cations where the MUXOUT and ADCIN need to be shortedtogether, the LTC2444/LTC2448 should be used becausethe MUXOUT and ADCIN are internally connected foroptimum performance.Output Data FormatThe LTC2444/LTC2445/LTC2448/LTC2449 serial outputdata stream is 32 bits long. The first 3 bits represent statusinformation indicating the sign and conversion state. Thenext 24 bits are the conversion result, MSB first. Theremaining 5 bits are sub LSBs beyond the 24-bit level thatmay be included in averaging or discarded without loss ofresolution. In the case of ultrahigh resolution modes,more than 24 effective bits of performance are possible(see Table 5). Under these conditions, sub LSBs areincluded in the conversion result and represent usefulinformation beyond the 24-bit level. The third and fourthbit together are also used to indicate an underrangecondition (the differential input voltage is below –FS) or anoverrange condition (the differential input voltage is above+FS).UBit 31 (first output bit) is the end of conversion (EOC)indicator. This bit is available at the SDO pin during theconversion and sleep states whenever the CS pin is LOW.This bit is HIGH during the conversion and goes LOWwhen the conversion is complete.Bit 30 (second output bit) is a dummy bit (DMY) and isalways LOW.Bit 29 (third output bit) is the conversion result sign indi-cator (SIG). If VIN is >0, this bit is HIGH. If VIN is <0, thisbit is LOW.Bit 28 (fourth output bit) is the most significant bit (MSB)of the result. This bit in conjunction with Bit 29 alsoprovides the underrange or overrange indication. If bothBit 29 and Bit 28 are HIGH, the differential input voltage isabove +FS. If both Bit 29 and Bit 28 are LOW, thedifferential input voltage is below –FS.The function of these bits is summarized in Table 1.Table 1. LTC2444/LTC2445/LTC2448/LTC2449 Status BitsInput RangeVIN ≥ 0.5 • VREF0V ≤ VIN < 0.5 • VREF–0.5 • VREF ≤ VIN < 0VVIN < –0.5 • VREFBit 31Bit 30Bit 29Bit 28EOCDMYSIGMSB0000000011001010WUUBits 28-5 are the 24-bit conversion result MSB first.Bit 5 is the least significant bit (LSB).Bits 4-0 are sub LSBs below the 24-bit level. Bits 4-0 maybe included in averaging or discarded without loss ofresolution.Data is shifted out of the SDO pin under control of the serialclock (SCK), see Figure 3. Whenever CS is HIGH, SDOremains high impedance and SCK is ignored.In order to shift the conversion result out of the device, CSmust first be driven LOW. EOC is seen at the SDO pin of thedevice once CS is pulled LOW. EOC changes real time fromHIGH to LOW at the completion of a conversion. Thissignal may be used as an interrupt for an externalmicrocontroller. Bit 31 (EOC) can be captured on the firstrising edge of SCK. Bit 30 is shifted out of the device on the sn2444589 2444589fs
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LTC2444/LTC2445/ LTC2448/LTC2449APPLICATIOS IFORATIOCS1SCK23456789101112131432SDI10ENSGLODDBIT 31BIT 30BIT 29BIT 28BIT 27BIT 26BIT 25BIT 24BIT 23BIT 22BIT 21SDOHi-ZEOC“0”SIGMSBBUSY2444 F04Figure 3. SDI Speed/Resolution, Channel Selection, and Data Output Timingfirst falling edge of SCK. The final data bit (Bit 0) is shiftedout on the falling edge of the 31st SCK and may be latchedon the rising edge of the 32nd SCK pulse. On the fallingedge of the 32nd SCK pulse, SDO goes HIGH indicating theinitiation of a new conversion cycle. This bit serves as EOC(Bit 31) for the next conversion cycle. Table 2 summarizesthe output data format.As long as the voltage on the IN+ and IN– pins is maintainedwithin the –0.3V to (VCC + 0.3V) absolute maximumoperating range, a conversion result is generated for anydifferential input voltage VIN from –FS = –0.5 • VREF to+FS = 0.5 • VREF. For differential input voltages greater than+FS, the conversion result is clamped to the value corre-sponding to the +FS + 1LSB. For differential input voltagesbelow –FS, the conversion result is clamped to the valuecorresponding to –FS – 1LSB.Table 2. LTC2444/LTC2445/LTC2448/LTC2449 Output Data FormatDifferential Input VoltageVIN*VIN* ≥ 0.5 • VREF**0.5 • VREF**–1LSB0.25 • VREF**0.25 • VREF**–1LSB0–1LSB–0.25 • VREF**–0.25 • VREF**–1LSB–0.5 • VREF**VIN* < –0.5 • VREF**Bit 31EOC0000000000Bit 30DMY0000000000Bit 29SIG1111100000Bit 28MSB1000011110Bit 270110011001Bit 260101010101Bit 250101010101……………………………Bit 00101010101 sn2444589 2444589fs*The differential input voltage VIN = IN+ – IN–. **The differential reference voltage VREF = REF+ – REF–.10
UA2A1A0OSR3OSR2OSR1OSR0TWOXBIT 0LSBHi-ZBIT 20BIT 19WUU SERIAL INTERFACE PINSThe LTC2444/LTC2445/LTC2448/LTC2449 transmit theconversion results and receive the start of conversioncommand through a synchronous 3- or 4-wire interface.During the conversion and sleep states, this interface canbe used to assess the converter status and during thedata output state it is used to read the conversion resultand program the speed, resolution and input channel.Serial Clock Input/Output (SCK)The serial clock signal present on SCK (Pin 38) is used tosynchronize the data transfer. Each bit of data is shifted outthe SDO pin on the falling edge of the serial clock.In the Internal SCK mode of operation, the SCK pin is anoutput and the LTC2444/LTC2445/LTC2448/LTC2449 cre-ate their own serial clock. In the External SCK mode ofoperation, the SCK pin is used as input. The internal or元器件交易网www.cecb2b.com
LTC2444/LTC2445/LTC2448/LTC2449APPLICATIO S I FOR ATIOexternal SCK mode is selected by tying EXT (Pin 3) LOWfor external SCK and HIGH for internal SCK.Serial Data Output (SDO)The serial data output pin, SDO (Pin 37), provides theresult of the last conversion as a serial bit stream (MSBfirst) during the data output state. In addition, the SDO pinis used as an end of conversion indicator during theconversion and sleep states.When CS (Pin 36) is HIGH, the SDO driver is switched toa high impedance state. This allows sharing the serialinterface with other devices. If CS is LOW during theconvert or sleep state, SDO will output EOC. If CS is LOWduring the conversion phase, the EOC bit appears HIGH onthe SDO pin. Once the conversion is complete, EOC goesLOW. The device remains in the sleep state until the firstrising edge of SCK occurs while CS = LOW.Chip Select Input (CS)The active LOW chip select, CS (Pin 36), is used to test theconversion status and to enable the data output transfer asdescribed in the previous sections.In addition, the CS signal can be used to trigger a newconversion cycle before the entire serial data transfer hasbeen completed. The LTC2444/LTC2445/LTC2448/LTC2449 will abort any serial data transfer in progress andstart a new conversion cycle anytime a LOW-to-HIGHtransition is detected at the CS pin after the converter hasentered the data output state.Serial Data Input (SDI)The serial data input (SDI, Pin 34) is used to select thespeed/resolution and input channel of the LTC2444/LTC2445/LTC2448/LTC2449. SDI is programmed by aserial input data stream under the control of SCK duringthe data output cycle, see Figure 3.Initially, after powering up, the device performs a conver-sion with IN+ = CH0, IN– = CH1, OSR = 256 (output rateUnominally 880Hz), and 1X speedup mode (no Latency).Once this first conversion is complete, the device entersthe sleep state and is ready to output the conversion resultand receive the serial data input stream programming thespeed/resolution and input channel for the next conver-sion. At the conclusion of each conversion cycle, thedevice enters this state.In order to change the speed/resolution or input channel,the first 3 bits shifted into the device are 101. This iscompatible with the programming sequence of theLTC2414/LTC2418. If the sequence is set to 000 or 100,the following input data is ignored (don’t care) and thepreviously selected speed/resolution and channel remainvalid for the next conversion. Combinations other than101, 100, and 000 of the 3 control bits should be avoided.If the first 3 bits shifted into the device are 101, then thefollowing 5 bits select the input channel for the followingconversion (see Tables 3 and 4). The next 5 bits select thespeed/resolution and mode 1X (no Latency) 2X (doubleoutput rate with one conversion latency), see Table 5. Ifthese 5 bits are set to all 0’s, the previous speed remainsselected for the next conversion. This is useful in applica-tions requiring a fixed output rate/resolution but need tochange the input channel. In this case, the timing and inputsequence is compatible with the LTC2414/LTC2418.When an update operation is initiated (the first 3 bits are101) the first 5 bits are the channel address. The firstbit, SGL, determines if the input selection is differential(SGL = 0) or single-ended (SGL = 1). For SGL = 0, twoadjacent channels can be selected to form a differentialinput. For SGL = 1, one of 8 channels (LTC2444/LTC2445)or one of 16 channels (LTC2448/LTC2449) is selected asthe positive input. The negative input is COM for all singleended operations. The remaining 4 bits (ODD, A2, A1, A0)determine which channel is selected. The LTC2448/LTC2449 use all 4 bits to select one of 16 different inputchannels (see table 3) while in the case of the LTC2444/LTC2445, A2 is always 0, and the remaining 3 bits selectone of 8 different input channels (see Table 4). sn2444589 2444589fs
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LTC2444/LTC2445/LTC2448/LTC2449APPLICATIOS IFORATIOTable 3. Channel Selection for the LTC2448/LTC2449MUX ADDRESSODD/SGL*00000000000000001111111111111111SIGN00000000111111110000000011111111A2A1A0000011110000111100001111000011110011001100110011001100110011001101010101010101010101010101010101IN+IN+IN+IN+IN+IN+IN+IN+IN+IN+IN+IN+IN+IN+IN+IN+IN–IN+IN–IN+IN–IN+IN–IN+IN–IN+IN–IN+IN–IN+IN–IN+IN–IN–IN–IN–IN–IN–IN–IN–IN–IN–IN–IN–IN–IN–IN–IN–0IN+1IN–IN+IN–IN+IN–IN+IN–IN+IN–IN+IN–IN+IN–IN+IN–23456789101112131415COMCHANNEL SELECTION*Default at power up12
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LTC2444/LTC2445/LTC2448/LTC2449APPLICATIOS IFORATIOMUX ADDRESSODD/SGLSIGNA2A1*0000000000010001010001000101010110001000100110011100110011011101*Default at power upTable 4. Channel Selection for the LTC2444/LTC2445 (Bit A2 Should Always Be 0)CHANNEL SELECTIONA001010101010101010IN+1IN–2IN+3IN–IN+IN–IN+IN–IN+IN–IN+IN+IN+IN+IN+IN+IN+IN+IN+IN–IN+IN–IN–IN–IN–IN–IN–IN–IN–IN–IN+IN–4567COMU sn2444589 2444589fs
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LTC2444/LTC2445/LTC2448/LTC2449APPLICATIO S I FOR ATIOOSR3OSR2OSR1OSR0Table 5. LTC2444/LTC2445/LTC2448/LTC2449 Speed/Resolution Selection CONVERSION RATERMSRMSTWOXINTERNALEXTERNALNOISENOISEENOBENOB9MHz10.24MHzLTC2444/LTC2445/LTC2444/LTC2445/ClockClockLTC2448LTC2449LTC2448LTC24490Keep Previous Speed/Resolution03.52kHz4kHz23µV23µV171701.76kHz2kHz4.4µV3.5µV20.120.10880Hz1kHz2.8µV2µV20.821.30440Hz500Hz2µV1.4µV21.321.80220Hz250Hz1.4µV1µV21.822.40110Hz125Hz1.1µV750nV22.122.9055Hz 62.5Hz720nV510nV22.723.4 027.5Hz31.25Hz530nV375nV23.224013.75Hz15.625Hz350nV250nV23.824.406.875Hz7.8125Hz280nV200nV24.124.61Keep Previous Speed/Resolution17.04kHz8kHz23µV23µV171713.52kHz4kHz4.4µV3.5µV20.120.111.76kHz2kHz2.8µV2µV20.821.3 1880Hz1kHz2µV1.4µV21.321.81440Hz500Hz1.4µV1µV21.822.41220Hz250Hz1.1µV750nV22.122.91110Hz125Hz720nV510nV22.723.4155Hz62.5Hz530nV375nV23.224127.5Hz31.25Hz350nV250nV23.824.4113.75Hz15.625Hz280nV200nV24.124.6OSRLATENCY000000001110000000011100001111001000011110010011001100100110011001010101010110101010101114
U64128256512102420484096819216384327686412825651210242048409681921638432768nonenonenonenonenonenonenonenonenonenone1 cycle1 cycle1 cycle1 cycle1 cycle1 cycle1 cycle1 cycle1 cycle1 cycle sn2444589 2444589fsWUU元器件交易网www.cecb2b.com
LTC2444/LTC2445/LTC2448/LTC2449APPLICATIO S I FOR ATIOSpeed Multiplier ModeIn addition to selecting the speed/resolution, a speedmultiplier mode is used to double the output rate whilemaintaining the selected resolution. The last bit of the 5-bitspeed/resolution control word (TWOX, see Table 5) deter-mines if the output rate is 1X (no speed increase) or 2X(double the selected speed).While operating in the 1X mode, the device combines twointernal conversions for each conversion result in order toremove the ADC offset. Every conversion cycle, the offsetand offset drift are transparently calibrated greatly simpli-fying the user interface. The resulting conversion resulthas no latency. The first conversion following a newlyselected speed/resolution and input channel is valid. Thisis identical to the operation of the LTC2440, LTC2414 andLTC2418.While operating in the 2X mode, the device performs arunning average of the last two conversion results. Thisautomatically removes the offset and drift of the devicewhile increasing the output rate by 2X. The resolution(noise) remains the same. If a new channel is selected, theconversion result is valid for all conversions after the firstconversion (one cycle latency). If a new speed/resolutionis selected, the first conversion result is valid but theresolution (noise) is a function of the running average. Allsubsequent conversion results are valid. If the mode ischanged from either 1X to 2X or 2X to 1X without changingthe resolution or channel, the first conversion result isvalid.If an external buffer/amplifier circuit is used for theLTC2445/LTC2449, the 2X mode can be used to increasethe settling time of the amplifier between readings. Whileoperating in the 2X mode, the multiplexer output (input tothe external buffer/amplifier) is switched at the end of eachconversion cycle. Prior to concluding the data out/in cycle,the analog multiplexer output is switched. This occurs atTable 6. LTC2444/LTC2445/LTC2448/LTC2449 Interface Timing ModesSCKSourceExternalExternalInternalInternalConversionCycleControlCS and SCKSCKCS ↓ContinuousDataOutputControlCS and SCKSCKCS ↓InternalConnectionandWaveformsFigures 4, 5Figure 6Figures 7, 8Figure 9 sn2444589 2444589fs
ConfigurationExternal SCK, Single Cycle ConversionExternal SCK, 2-Wire I/OInternal SCK, Single Cycle ConversionInternal SCK, 2-Wire I/O, Continuous ConversionUthe end of the conversion cycle (just prior to the dataoutput cycle) for auto calibration. The time required toread the conversion enables more settling time for theexternal buffer/amplifier. The offset/offset drift of theexternal amplifier is automatically removed by theconverter’s auto calibration sequence for both the 1X and2X speed modes.While operating in the 1X mode, if a new input channel isselected the multiplexer is switched on the falling edge ofthe 14th SCK (once the complete data input word isprogrammed). The remaining data output sequence timecan be used to allow the external buffer/amplifier to settle.BUSYThe BUSY output (Pin 2) is used to monitor the state ofconversion, data output and sleep cycle. While the part isconverting, the BUSY pin is HIGH. Once the conversion iscomplete, BUSY goes LOW indicating the conversion iscomplete and data out is ready. The part now enters theLOW power sleep state. BUSY remains LOW while data isshifted out of the device and SDI is shifted into the device.It goes HIGH at the conclusion of the data input/outputcycle indicating a new conversion has begun. This risingedge may be used to flag the completion of the data readcycle.SERIAL INTERFACE TIMING MODESThe LTC2444/LTC2445/LTC2448/LTC2449’s 3- or 4-wireinterface is SPI and MICROWIRE compatible. This inter-face offers several flexible modes of operation. These in-clude internal/external serial clock, 3- or 4-wire I/O, singlecycle conversion and autostart. The following sectionsdescribe each of these serial interface timing modes indetail. In all these cases, the converter can use the internaloscillator (FO = LOW) or an external oscillator connectedto the FO pin. Refer to Table6 for a summary.WUU15
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LTC2444/LTC2445/LTC2448/LTC2449APPLICATIO S I FOR ATIOExternal Serial Clock, Single Cycle Operation(SPI/MICROWIRE Compatible)This timing mode uses an external serial clock to shift outthe conversion result and a CS signal to monitor andcontrol the state of the conversion cycle, see Figure 4.The serial clock mode is selected by the EXT pin. To selectthe external serial clock mode, EXT must be tied low.The serial data output pin (SDO) is Hi-Z as long as CS isHIGH. At any time during the conversion cycle, CS may bepulled LOW in order to monitor the state of the converter.While CS is pulled LOW, EOC is output to the SDO pin.EOC=1 (BUSY = 1) while a conversion is in progress andEOC = 0 (BUSY = 0) if the device is in the sleep state.Independent of CS, the device automatically enters the lowpower sleep state once the conversion is complete.2.7V TO 5.5V1µF28VCCLTC2448REFERENCEVOLTAGE0.1V TO VCC•••293081516•••ANALOGINPUTS237CSTEST EOCSCK(EXTERNAL)TEST EOC123456789101112131432SDI10ENSGLBIT 31BIT 30BIT 29BIT 28BIT 27BIT 26BIT 25BIT 24BIT 23BIT 22BIT 21SDOHi-ZEOC“0”SIGMSBBUSYCONVERSIONSLEEPDATA OUTPUTCONVERSION2444 F05Figure 4. External Serial Clock, Single Cycle Operation sn2444589 2444589fs16
UWhen the device is in the sleep state (EOC = 0), itsconversion result is held in an internal static shift regis-ter. The device remains in the sleep state until the firstrising edge of SCK is seen. Data is shifted out the SDO pinon each falling edge of SCK. This enables external circuitryto latch the output on the rising edge of SCK. EOC can belatched on the first rising edge of SCK and the last bit ofthe conversion result can be latched on the 32nd risingedge of SCK. On the 32nd falling edge of SCK, the devicebegins a new conversion. SDO goes HIGH (EOC = 1) andBUSY goes HIGH indicating a conversion is in progress.At the conclusion of the data cycle, CS may remain LOWand EOC monitored as an end-of-conversion interrupt.Alternatively, CS may be driven HIGH setting SDO to Hi-Zand BUSY monitored for the completion of a conversion.FO35= EXTERNAL OSCILLATOR= INTERNAL OSCILLATORREF+REF–CH0•CH7CH8•CH15COM••••WUUSDISCK34384-WIRESPI INTERFACESDOCSBUSYGND373621,4,5,6,31,32,33ODDA2A1A0OSR3OSR2OSR1OSR0TWOXBIT 0LSBHi-ZBIT 20BIT 19元器件交易网www.cecb2b.com
LTC2444/LTC2445/LTC2448/LTC2449APPLICATIOS IFORATIOAs described above, CS may be pulled LOW at any time inorder to monitor the conversion status on the SDO pin.Typically, CS remains LOW during the data output state.However, the data output state may be aborted by pullingCS HIGH anytime between the fifth falling edge and the32nd falling edge of SCK, see Figure 5. On the rising edgeof CS, the device aborts the data output state and imme-diately initiates a new conversion. Thirteen serial inputdata bits are required in order to properly program thespeed/resolution and input channel. If the data output2.7V TO 5.5V1µF28VCCLTC2448REFERENCEVOLTAGE0.1V TO VCC•••293081516•••ANALOGINPUTS237CS1SCK(EXTERNAL)5123456TEST EOCSDIDON'T CAREBIT 31BIT 30BIT 29BIT 28BIT 27BIT 26BIT 25SDOHi-ZEOC“0”SIGMSBHi-ZBUSYDATA OUTPUTCONVERSIONSLEEPCONVERSIONDATA OUTPUTCONVERSIONSLEEP2444 F06Figure 5. External Serial Clock, Reduced Output Data LengthUsequence is aborted prior to the 13th rising edge of SCK,the new input data is ignored, and the previously selectedspeed/resolution and channel are used for the next con-version cycle. This is useful for systems not requiring all32 bits of output data, aborting an invalid conversioncycle or synchronizing the start of a conversion. If a newchannel is being programmed, the rising edge of CS mustcome after the 14th falling edge of SCK in order to storethe data input sequence.FO35= EXTERNAL OSCILLATOR= INTERNAL OSCILLATORREF+REF–CH0•CH7CH8•CH15COM••••WUUSDISCK34384-WIRESPI INTERFACESDOCSBUSYGND373621,4,5,6,31,32,33DON'T CAREDON'T CARE sn2444589 2444589fs17
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LTC2444/LTC2445/LTC2448/LTC2449APPLICATIOS IFORATIOExternal Serial Clock, 2-Wire I/OThis timing mode utilizes a 2-wire serial I/O interface. Theconversion result is shifted out of the device by an exter-nally generated serial clock (SCK) signal, see Figure 6. CSmay be permanently tied to ground, simplifying the userinterface or isolation barrier. The external serial clockmode is selected by tying EXT LOW.Since CS is tied LOW, the end-of-conversion (EOC) can becontinuously monitored at the SDO pin during the convertand sleep states. Conversely, BUSY (Pin 2) may be usedto monitor the status of the conversion cycle. EOC or BUSYmay be used as an interrupt to an external controller2.7V TO 5.5V1µF28VCCLTC2448REFERENCEVOLTAGE0.1V TO VCC•••293081516•••ANALOGINPUTS237CS1SCK(EXTERNAL)23456789101112131432SDIDON'T CARE10ENSGLBIT 31BIT 30BIT 29BIT 28BIT 27BIT 26BIT 25BIT 24BIT 23BIT 22BIT 21SDOEOC“0”SIGMSBBUSYCONVERSIONSLEEPDATA OUTPUTCONVERSION2444 F07Figure 6. External Serial Clock, CS = 0 Operation (2-Wire)18
Uindicating the conversion result is ready. EOC = 1(BUSY = 1) while the conversion is in progress andEOC=0 (BUSY = 0) once the conversion enters the lowpower sleep state. On the falling edge of EOC/BUSY, theconversion result is loaded into an internal static shiftregister. The device remains in the sleep state until thefirst rising edge of SCK. Data is shifted out the SDO pinon each falling edge of SCK enabling external circuitry tolatch data on the rising edge of SCK. EOC can be latchedon the first rising edge of SCK. On the 32nd falling edgeof SCK, SDO and BUSY go HIGH (EOC=1) indicating anew conversion has begun.FO35= EXTERNAL OSCILLATOR= INTERNAL OSCILLATORREF+REF–CH0•CH7CH8•CH15COM••••WUUSDISCK34384-WIRESPI INTERFACESDOCSBUSYGND373621,4,5,6,31,32,33ODDA2A1A0OSR3OSR2OSR1OSR0TWOXDON'T CAREBIT 0LSBBIT 20BIT 19 sn2444589 2444589fs元器件交易网www.cecb2b.com
LTC2444/LTC2445/LTC2448/LTC2449APPLICATIO S I FOR ATIOInternal Serial Clock, Single Cycle OperationThis timing mode uses an internal serial clock to shift outthe conversion result and a CS signal to monitor andcontrol the state of the conversion cycle, see Figure 7.In order to select the internal serial clock timing mode, theEXT pin must be tied HIGH.The serial data output pin (SDO) is Hi-Z as long as CS isHIGH. At any time during the conversion cycle, CS may bepulled LOW in order to monitor the state of the converter.Once CS is pulled LOW, SCK goes LOW and EOC is outputto the SDO pin. EOC = 1 while a conversion is in progressand EOC = 0 if the device is in the sleep state. Alternatively,BUSY (Pin 2) may be used to monitor the status of theconversion in progress. BUSY is HIGH during the conver-2.7V TO 5.5V281µFREFERENCEVOLTAGE0.1V TO VCC•••VCCLTC2448293081516•••REF+REF–CH0•CH7CH8•CH15COM••••ANALOGINPUTS237 LTC2444/LTC2445/LTC2448/LTC2449APPLICATIOS IFORATIOIf CS remains LOW longer than tEOCtest, the first risingedge of SCK will occur and the conversion result is seriallyshifted out of the SDO pin. The data output cycle begins onthis first rising edge of SCK and concludes after the 32ndrising edge. Data is shifted out the SDO pin on each fallingedge of SCK. The internally generated serial clock is outputto the SCK pin. This signal may be used to shift theconversion result into external circuitry. EOC can belatched on the first rising edge of SCK and the last bit of theconversion result on the 32nd rising edge of SCK. After the32nd rising edge, SDO goes HIGH (EOC = 1), SCK staysHIGH and a new conversion starts.Typically, CS remains LOW during the data output state.However, the data output state may be aborted by pullingCS HIGH anytime between the first and 32nd rising edge2.7V TO 5.5V1µF28VCCLTC2448REFERENCEVOLTAGE0.1V TO VCC•••ANALOGINPUTS••• 元器件交易网www.cecb2b.com LTC2444/LTC2445/LTC2448/LTC2449APPLICATIOS IFORATIONormal Mode Rejection and AntialiasingOne of the advantages delta-sigma ADCs offer over con-ventional ADCs is on-chip digital filtering. Combined witha large oversampling ratio, the LTC2444/LTC2445/LTC2448/LTC2449 significantly simplify antialiasing filterrequirements.The LTC2444/LTC2445/LTC2448/LTC2449’s speed/reso-lution is determined by the over sample ratio (OSR) of theon-chip digital filter. The OSR ranges from 64 for 3.5kHzoutput rate to 32,768 for 6.9Hz (in No Latency mode)output rate. The value of OSR and the sample rate fSdetermine the filter characteristics of the device. The firstNULL of the digital filter is at fN and multiples of fN wherefN = fS/OSR, see Figure 10 and Table 7. The rejection at thefrequency fN ±14% is better than 80dB, see Figure11.0SINC4 ENVELOPENORMAL MODE REJECTION (dB)–40–60–80–100–120–140NORMAL MODE REJECTION (dB)–20601202400180DIFFERENTIAL INPUT SIGNAL FREQUENCY (Hz)2440 F11Figure 10. LTC2444/LTC2445/LTC2448/LTC2449Normal Mode Rejection (Internal Oscillator)22 UTable 7. OSR vs Notch Frequency (fN) (with Internal OscillatorRunning at 9MHz)OSR6412825651210242048409681921638432768**Simultaneous 50/60Hz rejectionNOTCH (fN)28.16kHz14.08kHz7.04kHz3.52kHz1.76kHz880Hz440Hz220Hz110Hz55Hz–80–90–100–110–120–130–140474951535557596163DIFFERENTIAL INPUT SIGNAL FREQUENCY (Hz)2440 F12WUUFigure 11. LTC2444/LTC2445/LTC2448/LTC2449Normal Mode Rejection (Internal Oscillator) sn2444589 2444589fs元器件交易网www.cecb2b.com LTC2444/LTC2445/LTC2448/LTC2449APPLICATIO S I FOR ATIOIf FO is grounded, fS is set by the on-chip oscillator at1.8MHz ±5% (over supply and temperature variations). Atan OSR of 32,768, the first NULL is at fN = 55Hz and the nolatency output rate is fN/8 = 6.9Hz. At the maximum OSR,the noise performance of the device is 280nVRMS (LTC2444/LTC2448) and 200nVRMS (LTC2445/LTC2449) with betterthan 80dB rejection of 50Hz ±2% and 60Hz ±2%. Since theOSR is large (32,768) the wide band rejection is extremelylarge and the antialiasing requirements are simple. Thefirst multiple of fS occurs at 55Hz • 32,768 = 1.8MHz, seeFigure 12.The first NULL becomes fN = 7.04kHz with an OSR of 256(an output rate of 880Hz) and FO grounded. While theNULL has shifted, the sample rate remains constant. As aresult of constant modulator sampling rate, the linearity,offset and full-scale performance remains unchanged asdoes the first multiple of fS.The sample rate fS and NULL fN, may also be adjusted bydriving the FO pin with an external oscillator. The samplerate is fS = fEOSC/5, where fEOSC is the frequency of the0NORMAL MODE REJECTION (dB)–40–601.8MHz–80–100REJECTION > 120dB–120–140NORMAL MODE REJECTION (dB)–20100000020000000DIFFERENTIAL INPUT SIGNAL FREQUENCY (Hz)1440 F13Figure 12. LTC2444/LTC2445/LTC2448/LTC2449Normal Mode Rejection (Internal Oscillator)Uclock applied to FO. Combining a large OSR with a reducedsample rate leads to notch frequencies fN near DC whilemaintaining simple antialiasing requirements. A 100kHzclock applied to FO results in a NULL at 0.6Hz plus allharmonics up to 20kHz, see Figure 13. This is useful inapplications requiring digitalization of the DC componentof a noisy input signal and eliminates the need of placinga 0.6Hz filter in front of the ADC.An external oscillator operating from 100kHz to 20MHzcan be implemented using the LTC1799 (resistor setSOT-23 oscillator), see Figure 16. By floating pin 4 (DIV)of the LTC1799, the output oscillator frequency is:WUU⎛10k⎞fOSC=10MHz•⎜⎟⎝10•RSET⎠The normal mode rejection characteristic shown inFigure13 is achieved by applying the output of the LTC1799(with RSET = 100k) to the FO pin on the LTC2444/LTC2445/LTC2448/LTC2449 with SDI tied HIGH (OSR = 32768).0–20–40–60–80–100–120–1402461008DIFFERENTIAL INPUT SIGNAL FREQUENCY (Hz)2440 F14Figure 13. LTC2444/LTC2445/LTC2448/LTC2449 NormalMode Rejection (External Oscillator at 90kHz) sn2444589 2444589fs23 元器件交易网www.cecb2b.com LTC2444/LTC2445/LTC2448/LTC2449APPLICATIOS IFORATIOReduced Power OperationIn addition to adjusting the speed/resolution of theLTC2444/LTC2445/LTC2448/LTC2449, the speed/reso-lution/power dissipation may also be adjusted using theautomatic sleep mode. During the conversion cycle, theLTC2444/LTC2445/LTC2448/LTC2449 draw 8mA supplycurrent independent of the programmed speed. Once theconversion cycle is completed, the device automaticallyenters a low power sleep state drawing 8µA. The deviceremains in this state as long as CS is HIGH and data is notshifted out. By adjusting the duration of the sleep state(hold CS HIGH longer) and the duration of the conversioncycle (programming OSR) the DC power dissipation canbe reduced, see Figure 14.IREF+VREF+ILEAKIIN+VIN+VCCILEAKILEAKVCCILEAKVREF–ILEAKRSW (TYP)500ΩRSW (TYP)500ΩMUXVCCILEAKILEAKRSW (TYP)500ΩMUXCEQ5pF(TYP)(CEQ = 2pF SAMPLE CAP + PARASITICS)VCCILEAKRSW (TYP)500ΩIIN–VIN–IREF–Figure 15. LTC2444/LTC2448 Input StructureCONVERTERSTATESLEEPDATAOUTCONVERTCSSUPPLYCURRENT8µA8mAFigure 14. Reduced Power Timing Mode sn2444589 2444589fs24 UAverage Input CurrentThe LTC2444/LTC2448 switch the input and reference toa 2pF capacitor at a frequency of 1.8MHz. A simplifiedequivalent circuit is shown in Figure 15. The samplecapacitor for the LTC2445/LTC2449 is 4pF, and its aver-age input current is externally buffered from the inputsource.The average input and reference currents can be ex-pressed in terms of the equivalent input resistance of thesample capacitor, where: Req = 1/(fSW • Ceq)When using the internal oscillator, fSW is 1.8MHz and theequivalent resistance is approximately 110kΩ.2440 F16WUUSWITCHING FREQUENCYfSW = 1.8MHz INTERNAL OSCILLATORfSW = fEOSC/5 EXTERNAL OSCILLATORSLEEPDATAOUTCONVERTSLEEP8µA8mA8µA2440 F15元器件交易网www.cecb2b.com LTC2444/LTC2445/LTC2448/LTC2449APPLICATIOS IFORATIOInput Bandwidth and Frequency RejectionThe combined effect of the internal SINC4 digital filter andthe digital and analog autocalibration circuits determinesthe LTC2444/LTC2445/LTC2448/LTC2449 input band-width and rejection characteristics. The digital filter’sresponse can be adjusted by setting the oversample ratio(OSR) through the SPI interface or by supplying an exter-nal conversion clock to the fo pin.Table 8 lists the properties of the LTC2444/LTC2445/LTC2448/LTC2449 with various combinations ofoversample ratio and clock frequency. Understandingthese properties is the key to fine tuning the characteris-tics of the LTC2444/LTC2445/LTC2448/LTC2449 to theapplication.Maximum Conversion RateThe maximum conversion rate is the fastest possible rateat which conversions can be performed.Table 8Over-*RMS*RMSENOBMaximumFirst Notch Effective–3dBsampleNoiseNoise(VREF = 5V) Conversion Rate Frequency Noise BW point (Hz)RatioLTC2444/LTC2445/LTC2444/LTC2445/InternalExternalInternalExternalInternalExternalInternalExternal9MHz clockfo9MHz clockfo9MHz clockfo(OSR)LTC2448LTC2449LTC2449LTC24499MHz clockfo6423µV23µV17173515.6fo/256028125fo/3203148fo/57101696fo/5310128256512102420484096819216384327684.5µV2.8µV2µV1.4µV1.1µV720nV530nV350nV280nV3.5µV2µV1.4µV1µV750nV510nV375nV250nV200nV20.120.821.321.822.122.723.223.824.12021.321.822.422.923.42424.424.61757.8878.9439.5219.7109.954.927.513.76.9fo/5120fo/10240fo/20480fo/40960fo/81920fo/163840fo/327680fo/655360fo/131072014062.57031.33515.61757.8878.9439.5219.7109.954.9fo/640fo/1280fo/2560fo/5120fo/1020fo/2050fo/4100fo/8190fo/16380157478739419798.449.224.612.46.2fo/2860fo/1140fo/2280fo/4570fo/9140fo/18300fo/36600fo/73100fo/1463008484242121065326.513.26.63.3fo/10600fo/21200fo/42500fo/84900fo/170000fo/340000fo/679000fo/1358000fo/2717000*ADC noise increases by approximately √2 when OSR is decreased by a factor of 2 for OSR 32768 to OSR 256. The ADC noise at OSR 128 and OSR 64 include effects from internal modulator quantizationnoise.UFirst Notch FrequencyThis is the first notch in the SINC4 portion of the digitalfilter and depends on the fo clock frequency and theoversample ratio. Rejection at this frequency and itsmultiples (up to the modulator sample rate of 1.8MHz)exceeds 120dB. This is 8 times the maximum conversionrate.Effective Noise BandwidthThe LTC2444/LTC2445/LTC2448/LTC2449 has extremelygood input noise rejection from the first notch frequencyall the way out to the modulator sample rate (typically1.8MHz). Effective noise bandwidth is a measure of howthe ADC will reject wideband input noise up to the modu-lator sample rate. The example on the following pageshows how the noise rejection of the LTC2444/LTC2445/LTC2448/LTC2449 reduces the effective noise of an am-plifier driving its input. sn2444589 2444589fs WUU25 元器件交易网www.cecb2b.com LTC2444/LTC2445/LTC2448/LTC2449APPLICATIO S I FOR ATIOExample:If an amplifier (e.g. LT1219) driving the input of anLTC2444/LTC2445/LTC2448/LTC2449 has widebandnoise of 33nV/√Hz, band-limited to 1.8MHz, the totalnoise entering the ADC input is:33nV/√Hz • √1.8MHz = 44.3µV.When the ADC digitizes the input, its digital filter filters outthe wideband noise from the input signal. The noisereduction depends on the oversample ratio which definesthe effective bandwidth of the digital filter.At an oversample of 256, the noise bandwidth of the ADCis 787Hz which reduces the total amplifier noise to:33nV/√Hz • √787Hz = 0.93µV.The total noise is the RMS sum of this noise with the 2µVnoise of the ADC at OSR=256.√(0.93µV)2 + (2uV)2 = 2.2µV.Increasing the oversample ratio to 32768 reduces thenoise bandwidth of the ADC to 6.2Hz which reduces thetotal amplifier noise to:33nV/√Hz • √6.2Hz = 82nV.The total noise is the RMS sum of this noise with the 200nVnoise of the ADC at OSR = 32768.√(82nV)2 + (200nV)2 = 216nV.In this way, the digital filter with its variable oversamplingratio can greatly reduce the effects of external noisesources.4.5V TO 5.5V1µF28293089VCCBUSY2LTC1799V+OUT0.1µF3-WIRESPI INTERFACEGNDRSETLTC244835FOREF+38REF–SCK37CH0SDO36CH1CS•••3EXTGNDREFERENCEVOLTAGE0.1V TO VCCANALOG INPUT–0.5VREF TO0.5VREF1,4,5,6,31,32,33Figure 16. Simple External Clock Source sn2444589 2444589fs26 UAutomatic Offset Calibration of ExternalBuffers/AmplifiersThe LTC2445/LTC2449 enable an external amplifier to beinserted between the multiplexer output and the ADCinput. This enables one external buffer/amplifier circuit tobe shared between all 17 analog inputs (16 single-endedor 8 differential). The LTC2445/LTC2449 perform an inter-nal offset calibration every conversion cycle in order toremove the offset and drift of the ADC. This calibration isperformed through a combination of front end switchingand digital processing. Since the external amplifier isplaced between the multiplexer and the ADC, it is inside thecorrection loop. This results in automatic offset correctionand offset drift removal of the external amplifier.The LT1368 is an excellent amplifier for this function. Ithas rail-to-rail inputs and outputs, and it operates on asingle 5V supply. Its open-loop gain is 1M and its inputbias current is 10nA. It also requires at least a 0.1µF loadcapacitor for compensation. It is this feature that sets itapart from other amplifiers—the load capacitor attenu-ates sampling glitches from the LTC2445/LTC2449 ADCINterminals, allowing it to achieve full performance of theADC with high impedance at the multiplexer inputs.Another benefit of the LT1368 is that it can be poweredfrom supplies equal to or greater than that of the ADC. Thiscan allow the inputs to span the entire absolute maximumof GND – 0.3V to VCC + 0.3V. Using a positive supply of7.5V to 10V and a negative supply of –2.5 to –5V gives theamplifier plenty of headroom over the LTC2445/LTC2449input range.NCDIVSET24448 F17WUU元器件交易网www.cecb2b.com LTC2444/LTC2445/LTC2448/LTC2449PACKAGE DESCRIPTIOUUHF Package38-Lead Plastic QFN (5mm × 7mm)(Reference LTC DWG # 05-08-1701)0.70 ± 0.05PACKAGEOUTLINE0.25 ± 0.050.50 BSC5.20 ± 0.05 (2 SIDES)6.10 ± 0.05 (2 SIDES)7.50 ± 0.05 (2 SIDES)RECOMMENDED SOLDER PAD LAYOUT5.00 ± 0.10(2 SIDES)0.75 ± 0.050.00 – 0.053.15 ± 0.10(2 SIDES)0.4350.180.183738120.235.15 ± 0.10(2 SIDES)0.40 ± 0.100.200 REF0.25 ± 0.050.75 ± 0.050.200 REF0.00 – 0.050.50 BSCR = 0.115TYP(UH) QFN 03035.50 ± 0.05(2 SIDES)4.10 ± 0.05(2 SIDES)3.20 ± 0.05(2 SIDES)PIN 1TOP MARK(SEE NOTE 6)7.00 ± 0.10(2 SIDES)BOTTOM VIEW—EXPOSED PADNOTE:1. DRAWING CONFORMS TO JEDEC PACKAGE OUTLINE M0-220 VARIATION WHKD2. DRAWING NOT TO SCALE3. ALL DIMENSIONS ARE IN MILLIMETERS4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE5. EXPOSED PAD SHALL BE SOLDER PLATED6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE sn2444589 2444589fsInformation furnished by Linear Technology Corporation is believed to be accurate and reliable.However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.27 元器件交易网www.cecb2b.com LTC2444/LTC2445/LTC2448/LTC2449TYPICAL APPLICATIOUExternal Buffers Provide High Impedance Inputsand Amplifier Offsets are CancelledLTC244917CH0-CH15/COMHIGHSPEED∆Σ ADCSDISCKSDOCSMUXMUXOUTNMUXOUTP2–1/2 LT136810.22µF3+(EXTERNAL AMPLIFIERS)5V870.22µF2444589 TA056–+1/2 LT1368540VRELATED PARTSPART NUMBERLT1025LTC1043LTC1050LT1236A-5LT1461LTC1592LTC1655LTC1799LTC2053LTC2412LTC2415LTC2414/LTC2418LTC2430/LTC2431LTC2436-1LTC2440DESCRIPTIONMicropower Thermocouple Cold Junction CompensatorDual Precision Instrumentation Switched CapacitorBuilding BlockPrecision Chopper Stabilized Op AmpPrecision Bandgap Reference, 5VMicropower Series Reference, 2.5VUltraprecise 16-Bit SoftSpanTM DAC16-Bit Rail-to-Rail Micropower DACResistor Set SOT-23 OscillatorRail-to-Rail Instrumentation Amplifier2-Channel, Differential Input, 24-Bit, No Latency ∆Σ ADC1-Channel, Differential Input, 24-Bit, No Latency ∆Σ ADC4-/8-Channel, Differential Input, 24-Bit, No Latency ∆Σ ADC1-Channel, Differential Input, 20-Bit, No Latency ∆Σ ADC2-Channel, Differential Input, 16-Bit, No Latency ∆Σ ADC1-Channel, Differential Input, High Speed/Low Noise,24-Bit, No Latency ∆Σ ADCCOMMENTS80µA Supply Current, 0.5°C Initial AccuracyPrecise Charge, Balanced Switching, Low PowerNo External Components 5µV Offset, 1.6µVP-P Noise0.05% Max, 5ppm/°C Drift0.04% Max, 3ppm/°C Max DriftSix Programmable Output Ranges±1LSB DNL, 600µA, Internal Reference, SO-8Single Resistor Frequency Set10µV Offset with 50nV/°C Drift, 2.5µVP-P Noise 0.01Hz to 10Hz0.16ppm Noise, 2ppm INL, 200µA0.23ppm Noise, 2ppm INL, 2X Speed Up0.2ppm Noise, 2ppm INL, 200µA0.56ppm Noise, 3ppm INL, 200µA800nVRMS Noise, 0.12LBS INL, 0.006LBS Offset, 200µA2µVRMS Noise at 880Hz, 200nVRMS Noise at 6.9Hz,0.0005% INL, Up to 3.5kHz Output RateSoftSpan is a trademark of Linear Technology Corporation. sn2444589 2444589fs28 Linear Technology Corporation1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.comADCINNADCINP LT/TP 0304 1K • PRINTED IN USA © LINEAR TECHNOLOGY CORPORATION 2004 因篇幅问题不能全部显示，请点此查看更多更全内容