——多功能数字钟
专业： 通信c132 姓名： 苏莹洁138245 史晓威138241 指导老师： 安亚军
时间： 2015.12.26
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目录
1、设计目的·····················································3 2、设计系统环境·················································3 3、设计性能指标及功能···········································3 ···················································3 ···················································3 4、设计总体框图·················································3 5、底层文件设计··················································4 5.1秒计数器····················································4 5.2分钟计数器··················································4 5.3小时计数器··················································5 5.4整点报时驱动信号产生模块····································5 5.5驱动8位八段共阴扫描数码管的片选驱动信号输出模块··································································6 5.6驱动八段字形译码输出模块·····································6 6、顶层文件设计················································6 7、心得体会······················································7 附录（源程序）·····················································8
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1、设计目的
掌握各类计数器和分频器以及它们相连的设计方法；掌握多个数码管的原理与方法；掌握CPLD技术的层次化设计的方法；掌握使用VHDL语言的设计思想；对整个系统的设计有一个了解。 2、设计系统环境 （1）一台PC机；
（2）一套GW48型EDA实验开发系统硬件； （3）X+PLUS Ⅱ集成化的开发系统硬件。 3、设计性能指标及功能 3.1设计功能
1）具有时、分、秒计数显示功能，以24小时循环计时。 2）时钟计数显示时有LED灯的花样显示。 3）具有调节小时、分钟、秒及清零的功能。 4）具有整点报时功能。
1）时钟计数：完成时、分、秒的正确计时并且显示所计的数字；对秒、分 ——60进制计数，即从0到59循环计数，时钟——24进制计数，即从0到23循环计数，并且在数码管上显示数值。
2）时间设置：手动调节分钟、小时，可以对所设计的时钟任意调时间，这样使数字钟真正具有使用功能。我们可以通过实验板上的键7和键4进行任意的调整，因为我们用的时钟信号均是1HZ的，所以每LED灯变化一次就来一个脉冲，即计数一次。
3）清零功能：reset为复位键，低电平时实现清零功能，高电平时正常计数。可以根据我们自己任意时间的复位。
4）蜂鸣器在整点时有报时信号产生，蜂鸣器报警。产生“滴答.滴答”的报警声音。
5）LED灯在时钟显示时有花样显示信号产生。即根据进位情况，LED不停的闪烁，从而产生“花样”信号。 4、设计总体框图
根据总体方框图及各部分分配的功能可知，本系统可以由秒计数器、分钟计数器、小时计数器、整点报时、分的调整以及小时的调整和一个顶层文件构成。采用自顶向下的设计方法，子模块利用VHDL语言设计，顶层文件用原理图的设计方法。显示：小时采用24进制，而分钟均是采用6进制和10进制的组合。
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时调整分调整花样显示5、模块及模块功能
多功能数字钟中的时钟记数模块、驱动8位八段共阴扫描数码管的片选驱动信号输出模块、驱动八段字形译码输出模块、整点报时驱动信号产生模块。 5.1秒计数器
5 VHDL语言描述程序见附录
模块CNT60_2 该模块为60进制计数器，计时输出为秒的数值，在计时到59时送出进位信号CO,因为硬件有延时，所以模块CNT60_2在此模块变为00时加1，符合实际。
5秒计数器的仿真波形图
5.2分钟计数器
5 VHDL语言描述程序见附录
模块CNT60_1 该模块为60进制计数器，计时输出为分的数值，在EN信号有效且时钟到来时，计数器加1。在sb按下时，EN信号有效，计数值以秒的速度增加，从而实现对分钟的设置。
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控制单元 CLK信号 使能端信号 数字时钟时显示 分显示 秒显示 24进制 60进制 60进制 LED显示 整点报时
5分钟计数器的仿真波形图
5.3小时计数器
5VHDL语言描述程序见附录
模块CNT24 该模块为24进制计数器，计时输出为小时的数值，在EN信号有效且时钟到来时，计数器加1。在sa按下时，EN信号有效，计数值以秒的速
度增加，从而实现对时钟的设置。
5小时计数器的仿真波形图
5.4整点报时驱动信号产生模块 5VHDL语言描述程序见附录
该模块功能：在时钟信号（CLK）的作用下可以生成波形，SPEAK输出接扬声器， 以产生整点报时发声。
5整点报时驱动信号产生的仿真波形图
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5.5驱动8位八段共阴扫描数码管的片选驱动信号输出模块 5VHDL语言描述程序见附录
5驱动8位八段共阴扫描数码管的片选驱动信号输出的仿真波形图
5.6驱动八段字形译码输出模块 5VHDL语言描述程序见附录
该模块功能：信号输入后，模块驱动八段字形译码输出，A，B，C，D，E，F，G分别接八段共阴级数码管7个接口，即有字形输出。
5驱动八段字形译码输出的仿真波形图
6、顶层文件设计
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仿真是EDA技术的重要组成部分，也是对设计的电路进行功能和性能测试的有效手段。EDA工具提供了强大且与电路实时行为相吻合的精确硬件系统测试工具。在建立了波形文件、输入信号节点、波形参数、加输入信号激励电平并存盘之后，选择主菜单“MAX+plusII”中的仿真器项“Simulator”，弹出对话框之后单击“Start”进行仿真运算，完成之后就可以看到时序波形。图为总电路的时序图。
7、心得体会
1、在此次的数字钟设计过程中，更进一步地熟悉了芯片的结构及掌握了各芯的 工作原理及具体使用方法。
2、设计的模块要分块调试，免得所有部分都做完了再调试不知道哪出错了，毫无头绪。
3、在连接二十四进制，六十进制的进位的接法中，要求熟悉逻辑电路及其芯片各引脚的功能，那么在电路出错时便能准确地找出错误所在并及时纠正了.。
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附录（源程序）
library ieee; gic_1164.all;
use ieee.std_logic_unsigned.all; entity second is
port(reset,clk,setmin : in std_logic;
daout : out std_logic_vector(7 downto 0); enmin : out std_logic); end second;
architecture behav of second is
signal count : std_logic_vector(3 downto 0); signal counter : std_logic_vector(3 downto 0); signal carry_out1 : std_logic; signal carry_out2 : std_logic; begin
p1: process(reset,clk) begin
if reset='0' then count<=\"0000\"; counter<=\"0000\";
elsif(clk'event and clk='1') then if (counter<5) then if (count=9) then count<=\"0000\";
counter<=counter + 1; else
count<=count+1; end if;
carry_out1<='0'; else
if (count=9) then count<=\"0000\"; counter<=\"0000\"; carry_out1<='1'; else
count<=count+1; carry_out1<='0'; end if; end if; end if;
end process;
daout(7 downto 4)<=counter; daout(3 downto 0)<=count;
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enmin<=carry_out1 or setmin; end behav;
2.分钟计数器VHDL语言描述程序 library ieee;
use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all;
entity minute is
port(reset,clk,sethour: in std_logic;
daout : out std_logic_vector(7 downto 0); enhour : out std_logic); end minute;
architecture behav of minute is
signal count : std_logic_vector(3 downto 0); signal counter : std_logic_vector(3 downto 0); signal carry_out1 : std_logic; signal carry_out2 : std_logic; begin
p1: process(reset,clk) begin
if reset='0' then count<=\"0000\"; counter<=\"0000\";
elsif(clk'event and clk='1') then if (counter<5) then if (count=9) then count<=\"0000\";
counter<=counter + 1; else
count<=count+1; end if;
carry_out1<='0'; else
if (count=9) then count<=\"0000\"; counter<=\"0000\"; carry_out1<='1'; else
count<=count+1; carry_out1<='0'; end if; end if; end if;
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end process;
p2: process(clk) begin
if(clk'event and clk='0') then if (counter=0) then if (count=0) then carry_out2<='0'; end if; else
carry_out2<='1'; end if; end if;
end process;
daout(7 downto 4)<=counter; daout(3 downto 0)<=count;
enhour<=(carry_out1 and carry_out2) or sethour; end behav;
3.小时计数器VHDL语言描述程序 library ieee;
use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all;
entity hour is
port(reset,clk : in std_logic;
daout : out std_logic_vector(7 downto 0)); end hour;
architecture behav of hour is
signal count : std_logic_vector(3 downto 0); signal counter : std_logic_vector(3 downto 0); begin
p1: process(reset,clk) begin
if reset='0' then count<=\"0000\"; counter<=\"0000\";
elsif(clk'event and clk='1') then if (counter<2) then if (count=9) then count<=\"0000\";
counter<=counter + 1; else
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count<=count+1; end if; else
if (count=3) then count<=\"0000\"; counter<=\"0000\"; else
count<=count+1; end if; end if; end if;
end process;
daout(7 downto 4)<=counter; daout(3 downto 0)<=count; end behav;
VHDL语言描述程序 Library IEEE;
use IEEE.std_logic_1164.all; use ieee.std_logic_unsigned.all;
entity alert is Port(
clkspk : in std_logic;
second : in std_logic_vector(7 downto 0); minute : in std_logic_vector(7 downto 0); speak : out std_logic;
lamp : out std_logic_vector(8 downto 0)); end alert;
architecture behav of alert is signal divclkspk2 : std_logic; begin
p1: process(clkspk) begin
if (clkspk'event and clkspk='1') then divclkspk2<=not divclkspk2; end if;
end process;
p2: process(second,minute) begin
if (minute=\"01011001\") then case second is
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when \"01010001\"=>lamp<=\"000000001\";speak<=divclkspk2; when \"01010010\"=>lamp<=\"000000010\";speak<='0';
when \"01010011\"=>lamp<=\"000000100\";speak<=divclkspk2; when \"01010100\"=>lamp<=\"000001000\";speak<='0';
when \"01010101\"=>lamp<=\"000010000\";speak<=divclkspk2; when \"01010110\"=>lamp<=\"000100000\";speak<='0';
when \"01010111\"=>lamp<=\"001000000\";speak<=divclkspk2; when \"01011000\"=>lamp<=\"010000000\";speak<='0'; when \"01011001\"=>lamp<=\"100000000\";speak<=clkspk; when others=>lamp<=\"000000000\"; end case; end if;
end process; end behav;
5.驱动8位八段共阴扫描数码管的片选驱动信号输出VHDL语言描述程序library ieee;
use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all;
entity seltime is port(
ckdsp : in std_logic; reset : in std_logic;
second : in std_logic_vector(7 downto 0); minute : in std_logic_vector(7 downto 0); hour : in std_logic_vector(7 downto 0); daout : out std_logic_vector(3 downto 0); sel : out std_logic_vector(2 downto 0)); end seltime;
architecture behav of seltime is
signal sec : std_logic_vector(2 downto 0); begin
process(reset,ckdsp) begin
if(reset='0') then sec<=\"000\";
elsif(ckdsp'event and ckdsp='1') then if(sec=\"101\") then sec<=\"000\"; else
sec<=sec+1; end if;
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end if;
end process;
process(sec,second,minute,hour) begin case sec is
when \"000\"=>daout<=second(3 downto 0); when \"001\"=>daout<=second(7 downto 4); when \"010\"=>daout<=minute(3 downto 0); when \"011\"=>daout<=minute(7 downto 4); when \"100\"=>daout<=hour(3 downto 0); when \"101\"=>daout<=hour(7 downto 4); when others=>daout<=\"XXXX\"; end case; end process; sel<=sec; end behav;
VHDL语言描述程序 LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY DELED IS PORT(
S: IN STD_LOGIC_VECTOR(3 DOWNTO 0); A,B,C,D,E,F,G,H: OUT STD_LOGIC); END DELED;
ARCHITECTURE BEHAV OF DELED IS
SIGNAL DATA:STD_LOGIC_VECTOR(3 DOWNTO 0); SIGNAL DOUT:STD_LOGIC_VECTOR(7 DOWNTO 0); BEGIN DATA<=S;
PROCESS(DATA) BEGIN
CASE DATA IS
WHEN \"0000\"=>DOUT<=\"00111111\"; WHEN \"0001\"=>DOUT<=\"00000110\"; WHEN \"0010\"=>DOUT<=\"01011011\"; WHEN \"0011\"=>DOUT<=\"01001111\"; WHEN \"0100\"=>DOUT<=\"01100110\"; WHEN \"0101\"=>DOUT<=\"01101101\"; WHEN \"0110\"=>DOUT<=\"01111101\"; WHEN \"0111\"=>DOUT<=\"00000111\"; WHEN \"1000\"=>DOUT<=\"01111111\";
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WHEN \"1001\"=>DOUT<=\"01101111\"; WHEN \"1010\"=>DOUT<=\"01110111\"; WHEN \"1011\"=>DOUT<=\"01111100\"; WHEN \"1100\"=>DOUT<=\"00111001\"; WHEN \"1101\"=>DOUT<=\"01011110\"; WHEN \"1110\"=>DOUT<=\"01111001\"; WHEN \"1111\"=>DOUT<=\"01110001\"; WHEN OTHERS=>DOUT<=\"00000000\"; END CASE; END PROCESS; H<=DOUT(7); G<=DOUT(6); F<=DOUT(5); E<=DOUT(4); D<=DOUT(3); C<=DOUT(2); B<=DOUT(1); A<=DOUT(0); END BEHAV;
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