Design Guide FL1009 PCI Express to USB 3.0 Host Controller Revision 1.00 December 10, 2010 © Fresco Logic 2010 Revision History Revision Date Comment 1.0 June 7, 2010 Preliminary Release Page 0 of 24 Fresco Logic Design Guide FL1009 PCI Express to USB 3.0 Host Controller © Fresco Logic 2010 FL1009 PCI Express to USB 3.0 Host Controller Table of Contents 1. Introduction ................................................................................................................................................. 4 1.1 1.2 2. 3. USB ........................................................................................................................................... 5 PCI Express ............................................................................................................................... 5 Scope .......................................................................................................................................................... 6 Schematic Guide ......................................................................................................................................... 6 3.1 3.1.1 3.1.2 3.2 3.2.1 3.3 3.3.1 3.4 3.4.1 3.4.2 3.5 3.5.1 3.5.2 3.6 3.6.1 3.6.2 Power ......................................................................................................................................... 6 Power Rail ......................................................................................................................... 6 Ripple Require................................................................................................................... 6 PCIE ............................................................................................................................................ 7 PCIe Interface ................................................................................................................... 7 USB 3.0....................................................................................................................................... 7 USB3 Interface .................................................................................................................. 7 Over-Current .............................................................................................................................. 8 Over-Current Circuit ......................................................................................................... 8 Action ................................................................................................................................ 9 Voltage Drop .............................................................................................................................. 9 Worse-case Voltage Drop Topology ................................................................................... 9 Voltage Define................................................................................................................. 10 Other ........................................................................................................................................ 10 Crystal Select .................................................................................................................. 10 4. Indicator ......................................................................................... 錯誤! 尚未定義書籤。尚未定義書籤。 Layout Guide .............................................................................................................................................. 11 4.1 4.2 4.2.1 4.2.2 4.2.3 4.3 4.4 4.4.1 4.4.2 4.5 4.5.1 4.5.2 4.5.3 4.5.4 Key Considerations of High-speed PCB Design ...................................................................... 11 Printed Circuit Board (PCB) ...................................................................................................... 11 Material ............................................................................................................................ 11 Stack up .......................................................................................................................... 12 Characteristic Impedance ............................................................................................... 12 General Routing and Placement Routing Rules...................................................................... 13 Power Integrity ......................................................................................................................... 13 Decoupling Recommendation ......................................................................................... 13 Power Routing Rules ...................................................................................................... 14 Layout Guidelines .................................................................................................................... 14 USB 3.0 Layout Guidelines ............................................................................................. 14 PCIe Routing Guide on Motherboard ............................................................................. 15 PCIe Routing Guide on Adapter Card............................................................................. 16 PCIe Clock Routing Guides ............................................................................................ 17 Page 1 of 24 Fresco Logic Design Guide © Fresco Logic 2010 FL1009 PCI Express to USB 3.0 Host Controller 5. Conclusion ................................................................................................................................................ 19 Page 2 of 24 Fresco Logic Design Guide © Fresco Logic 2010 FL1009 PCI Express to USB 3.0 Host Controller List of Figures Figure 3.1 PCIe Interface .................................................................................................................................... 7 Figure 3.2 USB3 Interface ................................................................................................................................... 8 Figure 3.3 Over-Current Circuit ........................................................................................................................... 9 Figure 3.4 Worse-case Voltage Drop Topology ................................................................................................. 10 Figure 4.1 Stack up............................................................................................................................................ 12 Figure 4.2 USB 3.0 Layout Guidelines .............................................................................................................. 15 Figure 4.3 PCIe Clock Routing Guides .............................................................................................................. 17 List of Tables Table 3.1 Power Rail ............................................................................................................................................ 6 Table 3.2 Ripple Require ..................................................................................................................................... 6 Table 3.3 Over-Current Circuit ............................................................................................................................. 9 Table 3.4 Crystal Select ..................................................................................................................................... 10 Table 3.5 Operate Mode .................................................................................................................................... 10 Table 4.1 PCB Material ....................................................................................................................................... 11 Table 4.2 USB 3.0 Layout Guidelines ................................................................................................................ 14 Table 4.3 PCIe Layout Guide for Motherboard Topology .................................................................................. 15 Table 4.4 Layout Guide for on Adapter Card ..................................................................................................... 16 Table 4.5 PCIe clock routing guildes ................................................................................................................. 17 Page 3 of 24 Fresco Logic Design Guide © Fresco Logic 2010 FL1009 PCI Express to USB 3.0 Host Controller 1. Introduction This document provides a general design guideline for USB 3.0 chips by Fresco Logic. The information described in this document is based on the lab experiments and the simulations. It is desirable that the specific topologies, stack-up, and other parameters to the particular design are taken into consideration. For a complicated design, the simulation is required. Page 4 of 24 Fresco Logic Design Guide © Fresco Logic 2010 FL1009 PCI Express to USB 3.0 Host Controller 1.1 USB USB is a serial differential point-to-point interconnection. For more information on the USB standard, please refer to the Universal Serial Bus specification, at http://www.usb.org. 1.2 PCI Express PCI Express Base Specification 2.0 and the PCI Express Card Electromechanical Specification, revision 2.0 can be found from the website: www.pcisig.com. The PCI Express was designed to support 20 inches between components with standard FR4. Page 5 of 24 Fresco Logic Design Guide © Fresco Logic 2010 FL1009 PCI Express to USB 3.0 Host Controller 2. Scope This document provides guidelines for designing the layout and schematic of FL1009. The material covered can be separated two main categories: schematic guideline and layout guideline. 3. Schematic Guidelines Acknowledge following guidelines for schematic design is important. This section includes notices of Power, PCIE, USB, Over-Current, Voltage Drop and others. 3.1 Power 3.1.1 Power Rail Table 3.1 Power Rail DVCC33 DVCC10 PVCCA33X DVCC33X AVCC10 AVCC10X AVCC33X PVCCA25X DVCC10X Description Digital power Digital power USB PLL Power AUX Digital Power Analog Power AUX Analog Power AUX Analog Power PCIe PLL Power AUX Digital Power Typical 3.3V 1.05V 3.3V 3.3V 1.05V 1.05V 3.3V 2.5V 1.05V Torrance ± 10% ± 10% ± 5% ± 5% ± 5% ± 5% ± 5% ± 5% Current 3.1.2 Ripple Require Table 3.2 Ripple Require Power DVCC33 DVCC10 PVCC33X DVCC33X Page 6 of 24 Fresco Logic Design Guide © Fresco Logic 2010 FL1009 PCI Express to USB 3.0 Host Controller Ripple(p-p) Power Ripple(p-p) 100mV AVCC10 30mV 50mV AVCC10X 30mV 50mV AVCC33X 50mV 50mV DVCC10X 50mV 3.2 PCIE 3.2.1 PCIe Interface Here are notices: AC caps is required on TX traces 0.1uF (0402) is the best. Cards must strap PRSNT1n with PRSNT2n signal. (+) and (-) can reverse if layout cross. REXT is 12KΩ PCAP is 0.1uF. PCAP Figure 3.1 PCIe Interface 3.3 USB 3.0 3.3.1 USB3 Interface Here are notices: AC caps is required on SSTX pair. 0.1uF (0402) is the best. Page 7 of 24 Fresco Logic Design Guide © Fresco Logic 2010 FL1009 PCI Express to USB 3.0 Host Controller RREF is 12.1K SSCAP is 2.2nF VCC128 is 3.3uF Above components need added on each port. Crystal 12MHz or 30MHz. XCK -- 24 or 48MHz. XCK or crystal choose one. XCK Figure 3.2 USB3 Interface 3.4 Over-Current 3.4.1 Over-Current Circuit Page 8 of 24 Fresco Logic Design Guide © Fresco Logic 2010 FL1009 PCI Express to USB 3.0 Host Controller 3.3v R PPWRCTL Figure 3.3 Over-Current Circuit 3.4.2 Action (O) : Output pin from FL1009 (I): Input pin from FL1009 PPWRCTL is the control pin for PORT_PWR PPWRCTL = 0, FL1009 will not issue PORT_PWR signal. Table 3.3 Over-Current Circuit Status Normal Operation Over-Current Operation 5V 0V Low Low IN 5V OUT 5V PORT_PWR (O) High OC_ACT (I) High 3.5 VBus 3.5.1 Worse-case Voltage Drop Topology Page 9 of 24 Fresco Logic Design Guide © Fresco Logic 2010 FL1009 PCI Express to USB 3.0 Host Controller Figure 3.4 Worse-case Voltage Drop Topology 3.5.2 Voltage Define Normal 5V ± 5% souce (4.75V to 5.25V) Voltage supplied at connector (host) should be 4.45V to 5.25V The maximum current is 900mA The maximum drop voltage for connector is 27mV The maximum drop for cable is 171mV. 3.6 Others 3.6.1 Crystal Select Table 3.4 Crystal Select XTAL_SEL[1:0] 00 01 10 11 12MHz crystal oscillator to XSCI/XSCO 30MHz crystal oscillator to XSCI/XSCO 48MHz reference clock to XCK pin 24MHz reference clock to XCK pin XTAL_SEL connects to 3V3 for 1. 3.6.2 Indicator Table 3.5 Indicator Pin Mode Active U2LNKN USB2 low PCIELNKN PCIe low SSLNKN USB3 Low DATTXN TX low DATRXN RX low Page 10 of 24 Fresco Logic Design Guide © Fresco Logic 2010 FL1009 PCI Express to USB 3.0 Host Controller 4. Layout Guideline The following factors should be examined to determine whether or not the timing and signal quality requirements are both satisfied. Pre-layout analysis: Trace impedance Shape of Vias and trace routes Properties of connectors and cables Eye patterns of all topologies Crosstalk between circuit traces Post-layout analysis: 4.1 Key Considerations of High-speed PCB Design This section provides a design guideline based on the following key considerations: 1. 2. 3. 4. Maintain the trace impedance (Differential and single-ended) Avoid crosstalk into differential pairs from nearby signals Minimize the skew between traces within a differential pair Provide clean power for differential pair drivers and receivers The references and requirements discussed in this document will help users understand what an effective design is. Some design details, such as the board size and component layout will depend on the restrictions, these references offer additional useful information on good design practices that are applicable to a general PCB design. 4.2 Printed Circuit Board (PCB) 4.2.1 Material The typical board material is FR4. Table shows the characteristics of FR4. Please note that even though the same material may be used throughout a PCB, it is not necessarily uniform in its characteristics. Table 4.1 PCB Material Grade Permittivity dielectric constant,1 GHz FR4 4.2 ~ 4.5 Page 11 of 24 Fresco Logic Design Guide © Fresco Logic 2010 FL1009 PCI Express to USB 3.0 Host Controller Dielectric tangent,1 GHz 0.021 ~ 0.025 4.2.2 Stack up FL1009 based system can be designed with a 4-layer board. The stack-up is in the sequence of component layer, ground layer, power layer and solder layer. Note that routing any signal on either power or ground layer is not permitted. Based on 6 mils trace width and 60Ω±10% trace impedance. Figure 4.1 Stack up 4.2.3 Characteristic Impedance Stack up, trace width, and spacing between the traces of each pair should be determined in achieving differential impedance. Differential impedance can be calculated by using a 2-D field solver. However, it is strongly recommended to confirm the actual differential impedance with the board manufacturer. The higher the single-ended impedance becomes, the narrower the gap spacing between a pair of traces must be to meet the desired differential impedance. This leads to an increased coupling intensity and higher density of routing a pair of traces. The impedance control for a high single-ended impedance becomes more difficult. Page 12 of 24 Fresco Logic Design Guide © Fresco Logic 2010 FL1009 PCI Express to USB 3.0 Host Controller 4.3 General Routing and Placement Routing Rules Following general routing and placement guidelines when laying out a new design can help to minimize EMI problems and improve signal integrity. 1. Route differential pairs first with the minimum trace lengths. Maintain the maximum possible distance between the high-speed clocks/periodic signals to differential pairs and any connector leaving the PCB (i.e., I/O connectors, control and signal headers, or power connectors). 2. 3. 4. Differential pairs should be referred to a complete plane. Route differential pairs without Via and corners as possible to reduces reflections and impedance issue Do not route differential pairs traces under crystals, oscillators, clock synthesizers, magnetic devices, or ICs that use and/or duplicate clocks. 5. Keep the differential pair signals clear of the core logic set. High current transients are produced during internal state transitions and may be very difficult to filter out. 6. Length matching among differential pairs The total trace skew should be less than 5 mils (Recommended value) among differential pairs. The skew between the bonding wires inside the package also affects the total skew, as does skew between the PCB traces. When designing the differential PCB traces, users should take the differences of lengths at the bonding wires into consideration. 7. Stubs on the high-speed USB signals should be avoided, as stubs will cause the signal reflections and affect the signal integrity. 8. When it is necessary to turn 90°, use two 45° turns or an arc trace instead of making a single 90° turn. This reduces reflections on the signal by minimizing the impedance discontinuities. 9. Route all traces over continuous planes (Power or Ground), with no interruptions. Crossing over splits plane increases inductance and radiation levels by forcing a greater loop area. Likewise, avoid changing layers with USB differential pair traces as much as practical. It is preferable to change layers to avoid crossing a plane split. 10. Separate signal traces into similar categories and route similar signal traces together (Such as routing differential pairs together). 11. Prohibition of Crossing a split plane 12. Recommended spacing rule between traces of adjacent pairs: The differential pair needs to keep the width 2.5 times distance to other signal. 13. The net of RREF can keep away from any signal with high-speed clocks/periodic and avoid any via. 4.4 Power Integrity 4.4.1 Decoupling Recommendation Page 13 of 24 Fresco Logic Design Guide © Fresco Logic 2010 FL1009 PCI Express to USB 3.0 Host Controller This section describes the preliminary decoupling recommendations for USB 3.0 power. Please note that the recommendations provide the total minimum capacitance of each voltage plane. The recommended decoupling capacitance, ESR and ESL, of each voltage plane is the minimum aggregate value that can be achieved by adding multiple decoupling capacitors in parallel. Each decoupling capacitor should be placed with a one or two Vias to a voltage plane (Or plane fill area) and solid ground plane, so that the copper loss and inductance between the capacitor and nearby ball Via are negligible. Distribute the capacitors so that the entire power ball Via have decoupled nearby. It is recommended that the distance from the ball Via to decoupling be minimized. 4.4.2 Power Routing Rules Allow the minimum spacing of 2 mm between the power trace and other signal traces. Sensitive signal traces should not stride over the split needed for power-island separation. Place the bypass capacitors as close to the USB chip as possible for every pair of VDD and VSS pins The Via form power plane to bypass capacitor is located close to the bypass capacitor. Place the bulk capacitor near the power source. 4.5 Layout Guidelines 4.5.1 USB 3.0 Layout Guidelines Table 4.2 USB 3.0 Layout Guidelines Parameter Differential signal group Routing Guideline 1. 2. 3. Reference plane SSTX+/- SSRX+/- D+/- Comment Routing over an unbroken ground plane is preferred. If an unbroken ground plane is not available, route over an unbroken voltage plane. Characteristic trace impedance Differential pair spacing Total length (Differential trace) Length matching requirement Differential mode: 90 Ω nominal ±7 Ω Spacing from other groups or signal > 2.5 times for the minimum pair width from edge to edge < 8000 mils (Max.) Total allowable among a pair (Length skew between + and - signals of the pair) is 6 mils. Pair width is (Trace + Space + Trace) IC pad to USB connector through hold Page 14 of 24 Fresco Logic Design Guide © Fresco Logic 2010 FL1009 PCI Express toess to USB 3.0 Host Controller Parameter Via RREF Routing Guide VCC128 SSCAP AC Coupling No any Via on a on differential signal as possible Connect nnect to 12.1 KΩ ±1% accurate resistor Place thece the resistor as close as possible to chip and as possible sible as same layer with USB chip Avoid anid any toggle signal Capacitapacitance of 3.3 µF with low Equivalent Series Resistance nce (ESR) is R) is required Route asute as close as possible to the USB chip Capacitapacitance of 2.2 nF with low Equivalent Series Resistance nce (ESR) is R) is required Route asute as close as possible to the USB chip AC coupoupling capacitors must be located at the transmitter side. Capacitapacitance of 0.1 µF with low Equivalent Series Inductance nce (ESL) is L) is recommended Place ACce AC coupling capacitors as close as possible to the chip. TThe second option is to place the AC coupling capacitoracitors as close as possible to the USB connector. Figure 4.2 USB 3.0 Layout Guidelines 4.5.2 PCIe Routing GuiGuide on Motherboard Table 4.34.3 PCIe Layout Guide for Motherboard Topology Parameter Reference plane Characteristic trace impedance Microstrip trace width Microstrip trace spacing Routing GuideGuide Routing over thver the unbroken ground plane is preferred. If unbroken gron ground plane is not available, routinrouting over the unbroken voltage plane. Single-ended: 5ded: 50 Ω ± 15% Differential: 85 al: 85 Ω nominal ±15% 5 mils Between edgeedge-to-edge intra-pair (Between + (P) and - (N) pair): 8.7575 mils (Please refer to Note 2) Between other other pairs: > 25 mils edge to edge Transmit and reand receive pairs should be interleaved. If interleaving is nois not possible, then the spacing betweeetween inter-pairs should be increased to > 45 mils from edm edge to edge. The Page 15 of 24 Fresco Logic Design Guide © FL1009 PCI Express to USB 3.0 Host Controller edge-to-edge inter-pair is defined from the positive edge of one pair to the negative edge of next pair, or vice versa Stripline trace width Stripline trace spacing 5 mils Between + (P) and - (N) of pair: 8.75 mils, edge to edge Between other pairs: > 25 mils, edge to edge Transmit and receive pair should be interleaved. If interleaving is not possible, then the inter pair spacing should be increased to 45 mils from edge to edge. The edge-to-edge inter-pair is defined form the positive edge of one pair to the negative edge of next pair, or vice versa Group spacing AC coupling Total trace length Minimum edge-to-edge spacing from other groups: > 25 mils The AC coupling capacitors must be located at the transmitter. The required value range is from 75 nF to 200 nF. 1.0” (Min.) ~ 30.0” (Max.) For transmitter and receiver. The define of trace length is from the device signal pin to the AC coupling capacitor and from the AC coupling capacitor to the PCI Express device pin Length Matching Requirements Number of vias Total allowable between pair (Length skew between + and - signals of a pair) length mismatch on a system board must not exceed 25 mils. Length should be matched on a segment-by-segment basis. Each routing segment to be matched should be as close as possible. Total skew across all lanes must be less than 20 ns. 4 (Max.) 4.5.3 PCIe Routing Guide on Adapter Card Table 4.4 Layout Guide for on Adapter Card Parameter Reference plane Characteristic trace Microstrip trace width Microstrip trace spacing Routing Guide Routing over unbroken ground plane is preferred. If unbroken ground plane is not available, route over unbroken voltage plane. Single-ended: 60 Ω ± 15% 5 mils(Please refer to Note2) Intra pair: 8.75 mils edge to edge (Please refer to Note1) Between other pairs > 25 mils edge to edge Transmit and receive pair should be interleaved. If interleaving is not possible, the inter pair spacing should be increased to 50 mils from center to center. The center-to-center inter-pair is defined from the positive center of one pair to the negative center of next pair, or vice versa. Group spacing Spacing from other groups: > 25 mils Minimum spacing from edge to edge Trace length of received 1.0” (Min.) ~ 15” (Max.) differential pair Trace length from the device signal ball to the AC coupling capacitor of the transmit differential pair 0.25” (Min.) ~ 7” (Max.) impedance adapter card Differential: 100 Ω nominal ±15% Page 16 of 24 Fresco Logic Design Guide © Fresco Logic 2010 FL1009 PCI Express toess to USB 3.0 Host Controller Trace length MB2 from the AC coupling capacitor to the connector pins Length of matching requirements Number of vias Total alloal allowable between pair (Length skew between + and - sigsignals of a pair) length mismatchmatch on a system board must not exceed 60 mils. Length sgth should be matched on a segment-by-segment basis. Each rouh routing segment to be matched should be as close as posas possible. Two viaso vias per signal between the device package ball and the cthe connector pin Reducingducing the number of vias Impedanedance controlled vias (100% ±15%) preferred 1.0” (Min.) ~ 10.0” (Max.) 4.5.4 PCIe Clock RoutinRouting Guides Table 4.5 PCIe clock routing guildes Parameter Signal group Reference plane Characteristic trace impedance Trace width Serpentine spacing of a clock line from itselm itself Clock to other signal spacing Length matching requirements within differential pair Series resistor, Rs Shunt resistors, Rt Number of Vias 33 ± 5% 49.9 ± 1% 4 (Max.) Routing Guide REFCLKP, REFCLKN differential pairs Routing over the unbroken ground plane is preferpreferred. If the unbroken ground plane is not available, route over the unbr unbroken voltage plane. Single-ended: 50 Ω ± 15% Differential: 100 Ω nominal ±15% 5 mils (Please refer to Note 2) > 25 mils > 25 mils ± 5 mils Figure 4.3 PCIe Clock Routing Guides Notes: 1. Termination resistors are only nly required reon the system boards (Root Complex) lex) if the resistors are not already presented. The adapter cpter cards do not require the Rs and Rt resistors. Page 17 of 24 Fresco Logic Design Guide © FL1009 PCI Express to USB 3.0 Host Controller 2. The width and spacing recommendations of intra-pair do not have to be strictly adhered to, but it is very important to meet the given differential target impedance and specified tolerance. It is also very important to follow the inter-pair spacing recommendations. Page 18 of 24 Fresco Logic Design Guide © Fresco Logic 2010 FL1009 PCI Express to USB 3.0 Host Controller 5. Conclusion That the schematic and layout are followed the guidelines in this document should make the successful product with the FL1009. Page 19 of 24 Fresco Logic Design Guide © Fresco Logic 2010 FL1009 PCI Express to USB 3.0 Host Controller Layout Check List Signal Group USBCLK 12/30MHz,USBCLK 12/30MHz, /30MHz, 30 ppm 30 ppm Signal Group PCIe CLK PCIe CLK Signal Group USB RX+ , RX-USB RX+ , RX- , D+ , D-, D+ , D- USB TX+ , TX-USB TX+ , TX- Signal Group PCIe TX+ , TX-PCIe TX+ , TX- , RX+ , RX-, RX+ , RX- Signal Group UREF0, UREF1REF0, UREF1 0, UREF1 Explanation Trace Width=6 mils, Spacing=20 mils. Trace Width=6 mils, Spacing=20 mils. Explanation Trace Width=5 mils, Spacing=6 mils. Trace Width=5 mils, Spacing=6 mils. To others signal Spacing=25 mils. To others signal Spacing=25 mils. Reference to Ground. Reference to Ground. Length matching 5 mils. Length matching 5 mils. Explanation Trace Width=6 mils, Spacing=6 mils. Trace Width=6 mils, Spacing=6 mils. To others signal Spacing=45 mils. To others signal Spacing=45 mils. Reference to Ground. Reference to Ground. Length matching 5 mils. Length matching 5 mils. Total Length 8000 mils Total Length 8000 mils No any via on differential signal No any via on differential signal Trace Width=6 mils, Spacing=6 mils. Trace Width=6 mils, Spacing=6 mils. To others signal Spacing=45 mils. To others signal Spacing=45 mils. Reference to Ground. Reference to Ground. Capacitors 0.1uF, close to connector. apacitors 0.1uF, close to connector. Length matching 5 mils. Length matching 5 mils. Total Length 8000 mils Total Length 8000 mils No any via on differential signal No any via on differential signal Explanation Trace Width=5 mils, Spacing=6 mils.Trace Width=5 mils, Spacing=6 mils. Spacing=6 mils. To others signal Spacing=25 mils. To others signal Spacing=25 mils. Length matching 5 mils. Length matching 5 mils. Two vias on differential signal Two vias on differential signal Explanation Connect to 12.1 KΩ±Connect to 12.1 KΩ±1% accurate resistor.Ω±1% accurate resistor. 1% accurate resistor. Close to FL1009Close to FL1009 FL1009 Yes No No Yes No No Yes No No Yes No No Yes No No Page 20 of 24 Fresco Logic Design Guide © Fresco Logic 2010 FL1009 PCI Express to USB 3.0 Host Controller Signal Group UV128UV1280, UV12811280, UV1281 0, UV1281 Signal Group UCAP0, UCAP1CAP0, UCAP1 0, UCAP1 Signal Group AVCC1V0 AVCC1V0 Signal Group PVCCA33 PVCCA33 Signal Group PVCCA25 PVCCA25 Explanation Capacitance 3.3 uF with low ESR Capacitance 3.3 uF with low ESR Close to FL1009Close to FL1009 FL1009 Explanation Capacitance 2.2 nF with low ESR Capacitance 2.2 nF with low ESR Close to FL1009Close to FL1009 FL1009 Explanation Capacitance 10 uF, 1uF, 0.1uF, 1nF with Capacitance 10 uF, 1uF, 0.1uF, 1nF with 3mΩ 3mΩ ESR, Min ESL < 150pH ESR, Min ESL < 150pH Trace Width=20mils. Spacing = 80 mils. Trace Width=20mils. Spacing = 80 mils. Explanation Capacitance 3.3 Capacitance 3.3 uF, 0.1uF, 1nF with uF, 0.1uF, 1nF with 3mΩ3mΩ ESR, Min ESL < 150pH ESR, Min ESL < 150pH Trace Width=20 mils. Spacing = 80 mils. Trace Width=20 mils. Spacing = 80 mils. Explanation Capacitance 3.3 Capacitance 3.3 uF, 0.1uF, 1nF with uF, 0.1uF, 1nF with 3mΩESR, Min ESL < 150pH 3mΩESR, Min ESL < 150pH Trace Width=20 mils. Spacing = 80 mils.Trace Width=20 mils. Spacing = 80 mils. Width=20 mils. Spacing = 80 mils. Yes No No Yes No No Yes No No Yes No No Yes No No Page 21 of 24 Fresco Logic Design Guide © Fresco Logic 2010 Referenced Documents Titles of Documents datasheet_FL1009_v091 Page 22 of 24 Fresco Logic Design Guide FL1009 PCI Express to USB 3.0 Host Controller © Fresco Logic 2010 FL1009 PCI Express to USB 3.0 Host Controller Legal Disclaimer Information in this document is provided in connection with Fresco Logic, Inc. products. No license, express or implied, by estoppels or otherwise, to any intellectual property rights is granted by this document. Except as provided in Fresco Logic’s terms and conditions of sale for such products, Fresco Logic assumes no liability whatsoever, and Fresco Logic disclaims any express or implied warranty, relating to sale and/or use of Fresco Logic products, including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. This document provides technical information for the user. Fresco Logic, Inc. reserves the right to modify the information in this document as necessary. The customer should make sure that they have the most recent datasheet version. Fresco Logic, Inc. holds no responsibility for any errors that may appear in this document. Customers should take appropriate action to ensure their use of the products does not infringe upon any patents. Fresco Logic, Inc. respects valid patent right of third parties and does not infringe upon or assist others to infringe upon such rights. All information contained herein is subject to change without notice. Page 23 of 24 Fresco Logic Design Guide © Fresco Logic 2010