TLV5712.7 V TO 5.5 V, 1-CHANNEL, 8-BIT,PARALLEL ANALOG-TO-DIGITAL CONVERTERSLAS239A – SEPTEMBER 1999 – REVISED FEBRUARY 2000featuresapplicationsDFast Throughput Rate: 1.25 MSPS at 5 V, DDDDDDDDDDDDD 625 KSPS at 3 VWide Analog Input: 0 V to AVDDDifferential Nonlinearity Error: < ± 0.5 LSBIntegral Nonlinearity Error: < ± 0.5 LSBSingle 2.7-V to 5.5-V Supply OperationLow Power: 12 mW at 3 V and 35 mW at 5 VAuto Power Down of 1 mA MaxSoftware Power Down: 10 µA MaxInternal OSCHardware ConfigurableDSP and Microcontroller CompatibleParallel InterfaceBinary/Twos Complement OutputHardware Controlled Extended SamplingHardware or Software Start of ConversionDDDDDDMass Storage and HDDAutomotiveDigital ServosProcess ControlGeneral-Purpose DSPImage Sensor ProcessingDW OR PW PACKAGE(TOP VIEW)CSWRRDCLKDGNDDVDDINT/EOCDGNDDGNDD0D1D21234 56789101112242322212019181716151413descriptionNCAINAVDDAGNDREFMREFPCSTARTA1/D7A0/D6D5D4D3The TLV571 is an 8-bit data acquisition systemNC – No internal connectionthat combines a high-speed 8-bit ADC and aparallel interface. The device contains two on-chip control registers allowing control of software conversion startand power down via the bidirectional parallel port. The control registers can be set to a default mode using adummy RD while WR is tied low allowing the registers to be hardware configurable.The TLV571 operates from a single 2.7-V to 5.5-V power supply. It accepts an analog input range from 0 V toAVDD and digitizes the input at a maximum 1.25 MSPS throughput rate at 5 V. The power dissipations are only12mW with a 3-V supply or 35 mW with a 5-V supply. The device features an auto power-down mode thatautomatically powers down to 1 mA 50 ns after conversion is performed. In software power-down mode, theADC is further powered down to only 10 µA.Very high throughput rate, simple parallel interface, and low power consumption make the TLV571 an idealchoice for high-speed digital signal processing.AVAILABLE OPTIONSPACKAGETA–40°C to 85°C24 TSSOP(PW)TLV571IPW24 SOIC(DW)TLV571IDWPlease be aware that an important notice concerning availability, standard warranty, and use in critical applications ofTexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.PRODUCTION DATA information is current as of publication date.Products conform to specifications per the terms of Texas Instrumentsstandard warranty. Production processing does not necessarily includetesting of all parameters.Copyright © 2000, Texas Instruments IncorporatedPOST OFFICE BOX 655303 DALLAS, TEXAS 75265•1http://oneic.com/SLAS239A – SEPTEMBER 1999 – REVISED FEBRUARY 2000TLV5712.7 V TO 5.5 V, 1-CHANNEL, 8-BIT,PARALLEL ANALOG-TO-DIGITAL CONVERTERfunctional block diagramAVDDAINREFPREFMDVDD 8-BITSAR ADCInternalClockCLKThreeStateLatchD0 – D5D6/A0D7/A1MUXCSRDWRCSTARTInput Registersand Control LogicINT/EOCAGNDDGNDTerminal FunctionsTERMINALNAMENO.AGNDAINAVDDA0/D6A1/D7CLKCSCSTARTDGNDDVDDD0 – D5INT/EOCNCRDREFMREFPWR212322161741185, 8, 9610–15724320192IIIII/OOI/OI/OIIIII/OAnalog groundADC analog inputAnalog supply voltage, 2.7 V to 5.5 VBidirectional 3-state data bus. D6/A0 along with D7/A1 is used as address lines to access CR0 and CR1 forinitialization.Bidirectional 3-state data bus. D7/A1 along with D6/A0 is used as address lines to access CR0 and CR1 forinitialization.External clock inputChip select. A logic low on CS enables the TLV571.Hardware sample and conversion start input. The falling edge of CSTART starts sampling and the rising edgeof CSTART starts conversion.Digital groundDigital supply voltage, 2.7 V to 5.5 VBidirectional 3-state data busEnd-of-conversion/interruptNot connectedRead data. A falling edge on RD enables a read operation on the data bus when CS is low.Lower reference voltage (nominally ground). REFM must be supplied or REFM pin must be grounded.Upper reference voltage (nominally AVDD). The maximum input voltage range is determined by the differencebetween the voltage applied to REFP and REFM.Write data. A rising edge on the WR latches in configuration data when CS is low. When using softwareconversion start, a rising edge on WR also initiates an internal sampling start pulse. When WR is tied to ground,the ADC in nonprogrammable (hardware configuration mode).DESCRIPTION2POST OFFICE BOX 655303 DALLAS, TEXAS 75265•http://oneic.com/ TLV5712.7 V TO 5.5 V, 1-CHANNEL, 8-BIT,PARALLEL ANALOG-TO-DIGITAL CONVERTERSLAS239A – SEPTEMBER 1999 – REVISED FEBRUARY 2000detailed descriptionanalog-to-digital SAR converterAinChargeRedistributionDAC_+SARRegisterADC CodeREFMControlLogicFigure 1The TLV571 is a successive-approximation ADC utilizing a charge redistribution DAC. Figure 1 shows asimplified version of the ADC.The sampling capacitor acquires the signal on Ain during the sampling period. When the conversion processstarts, the SAR control logic and charge redistribution DAC are used to add and subtract fixed amounts of chargefrom the sampling capacitor to bring the comparator into a balanced condition. When the comparator isbalanced, the conversion is complete and the ADC output code is generated.sampling frequency, fsThe TLV571 requires 16 CLKs for each conversion, therefore the equivalent maximum sampling frequencyachievable with a given CLK frequency is:fs(max) = (1/16) fCLKThe TLV571 is software configurable. The first two MSB bits, D(7,6) are used to address which register to set.The remaining six bits are used as control data bits. There are two control registers, CR0 and CR1, that are userconfigurable. All of the register bits are written to the control register during write cycles. A description of thecontrol registers is shown in Figure 2.POST OFFICE BOX 655303 DALLAS, TEXAS 75265•3http://oneic.com/SLAS239A – SEPTEMBER 1999 – REVISED FEBRUARY 2000TLV5712.7 V TO 5.5 V, 1-CHANNEL, 8-BIT,PARALLEL ANALOG-TO-DIGITAL CONVERTERdetailed description (continued)control registersA1A0D5D4D3D2D1D0 A(1:0)=00Control Register Zero (CR0)D5D4D3STARTSELPROGEOCCLKSEL0:0:HARDWAREINTSTART(CSTART)1:EOC1:SOFTWARESTART0:InternalClock1:ExternalClockD2SWPWDN0:NORMAL1:PowerdownD1Don’t CareD0Don’t CareDon’t CareDon’t CareA(1:0)=01Control Register One (CR1)D5D4D1D3D2ReservedOSCSPD0 Reserved0 ReservedOUTCODE0:ReservedBitAlwaysWrite 00:INT. OSC.SLOW1:INT. OSC.FAST0:ReservedBitAlwaysWrite 00:ReservedBit,AlwaysWrite 00:BinaryD0Reserved0:ReservedBit,AlwaysWrite 01: 2’sComplementFigure 2. Input Data Formathardware configuration optionThe TLV571 can configure itself. This option is enabled when the WR pin is tied to ground and a dummy RDsignal is applied. The ADC is now fully configured. Zeros or default values are applied to both control registers.The ADC is configured ideally for 3-V operation, which means the internal OSC is set at 10 MHz and hardwarestart of conversion using CSTART.ADC conversion modesThe TLV571 provides two start of conversion modes. Table 1 explains these modes in more detail.4POST OFFICE BOX 655303 DALLAS, TEXAS 75265•http://oneic.com/ TLV5712.7 V TO 5.5 V, 1-CHANNEL, 8-BIT,PARALLEL ANALOG-TO-DIGITAL CONVERTERSLAS239A – SEPTEMBER 1999 – REVISED FEBRUARY 2000detailed description (continued)Table 1. Conversion ModesSTART OFCONVERSIONHardware start(CSTART)CR0.D5 = 0•••••OPERATIONCOMMENTS – FOR INPUTRepeated conversions from AINCSTART rising edge must be appliedCSTART falling edge to start samplinga minimum of 5 ns before or after CLKrising edge.CSTART rising edge to start conversionIf in INT mode, one INT pulse generated after each conversionIf in EOC mode, EOC will go high to low at start of conversion, and return highat end of conversion.Software startCR0.D5 = 1•Repeated conversions from AINWith external clock, WR and RD rising•WR rising edge to start sampling initially. Thereafter, sampling occurs at theedge must be a minimum 5 ns beforeor after CLK rising edge.rising edge of RD.•Conversion begins after 6 clocks after sampling has begun. Thereafter, if in INTmode, one INT pulse generated after each conversion•If in EOC mode, EOC will go high to low at start of conversion and return high atend of conversion.configure the deviceThe device can be configured by writing to control registers CR0 and CR1.Table 2. TLV571 Programming ExamplesREGISTEREXAMPLE1CR0CR1EXAMPLE2CR0CR10001001010100100Power down, EXT OSC2’s complement output0001000000000000Normal, INT OSCBinaryINDEXD7D6D5D4D3D2D1D0COMMENTpower downThe TLV571 offers two power down modes, auto power down and software power down. This device willautomatically proceed to auto power down mode if RD is not present one clock after conversion. Software powerdown is controlled directly by the user by pulling CS to DVDD.Table 3. Power Down ModesPARAMETERS/MODESMaximum power down dissipation currentComparatorClock bufferControl registersMinimum power down timeMinimum resume timeAUTO POWER DOWN1 mAPower downPower downSaved1 CLK1 CLKSOFTWARE POWER DOWN(CS = DVDD)10 µAPower downPower downSaved2 CLK2 CLKPOST OFFICE BOX 655303 DALLAS, TEXAS 75265•5http://oneic.com/SLAS239A – SEPTEMBER 1999 – REVISED FEBRUARY 2000TLV5712.7 V TO 5.5 V, 1-CHANNEL, 8-BIT,PARALLEL ANALOG-TO-DIGITAL CONVERTERdetailed description (continued)reference voltage input The TLV571 has two reference input pins: REFP and REFM. The voltage levels applied to these pins establishthe upper and lower limits of the analog inputs to produce a full-scale and zero-scale reading respectively. Thevalues of REFP, REFM, and the analog input should not exceed the positive supply or be less than GNDconsistent with the specified absolute maximum ratings. The digital output is at full scale when the input signalis equal to or higher than REFP and is at zero when the input signal is equal to or lower than REFM.sampling/conversionAll sampling, conversion, and data output in the device are started by a trigger. This could be the RD, WR, orCSTART signal depending on the mode of conversion and configuration. The rising edge of RD, WR, andCSTART signal are extremely important, since they are used to start the conversion. These edges need to stayclose to the rising edge of the external clock (if it is used as CLK). The minimum setup and hold time with respectto the rising edge of the external clock should be 5 ns minimum. When the internal clock is used, this is not anissue since these two edges will start the internal clock automatically. Therefore, the setup time is always met.Software controlled sampling lasts 6 clock cycles. This is done via the CLK input or the internal oscillator ifenabled. The input clock frequency can be 1 MHz to 20 MHz, translating into a sampling time from 0.6 µs to0.3µs. The internal oscillator frequency is 9 MHz minimum (ocillator frequency is between 9 MHz to 22 MHz),translating into a sampling time from 0.6 µs to 0.3µs. Conversion begins immediately after sampling and lasts10 clock cycles. This is again done using the external clock input (1 MHz–20 MHz) or the internal oscillator (9 MHz minimum) if enabled. Hardware controlled sampling, via CSTART, begins on falling CSTART lasts thelength of the active CSTART signal. This allows more control over the sampling time, which is useful whensampling sources with large output impedances. On rising CSTART, conversion begins. Conversion inhardware controlled mode also lasts 10 clock cycles. This is done using the external clock input (1 MHz–20 MHz)or the internal oscillator (9 MHz minimum) as is the case in software controlled mode.ExtClkth(WRL_EXTCLKH) ≥5 nstsu(WRH_EXTCLKH) ≥5 nsWRORth(RDL_EXTCLKH) ≥5 nstsu(RDH_EXTCLKH) ≥5 nsRDORth(CSTARTL_EXTCLKH) ≥5 nstd(EXTCLK_CSTARTL) ≥5 nsCSTARTNOTE:tsu = setup time, th = hold timetsu(CSTARTH_EXTCLKH)≥5 nsFigure 3. Trigger Timing – Software Start Mode Using External Clock6POST OFFICE BOX 655303 DALLAS, TEXAS 75265•http://oneic.com/ TLV5712.7 V TO 5.5 V, 1-CHANNEL, 8-BIT,PARALLEL ANALOG-TO-DIGITAL CONVERTERSLAS239A – SEPTEMBER 1999 – REVISED FEBRUARY 2000start of conversion mechanismThere are two ways to convert data: hardware and software. In the hardware conversion mode the ADC beginssampling at the falling edge of CSTART and begins conversion at the rising edge of CSTART. Software startmode ADC samples for 6 clocks, then conversion occurs for ten clocks. The total sampling and conversionprocess lasts only 16 clocks in this case. If RD is not detected during the next clock cycle, the ADC automaticallyproceeds to a power-down state. Data is valid on the rising edge of INT in both conversion modes.hardware CSTART conversionexternal clockWith CS low and WR low, data is written into the ADC. The sampling begins at the falling edge of CSTART andconversion begins at the rising edge of CSTART. At the end of conversion, EOC goes from low to high, tellingthe host that conversion is ready to be read out. The external clock is active and is used as the reference at alltimes. With this mode, it is required that CSTART is not applied at the rising edge of the clock (see Figure 4).POST OFFICE BOX 655303 DALLAS, TEXAS 75265•7http://oneic.com/http://oneic.com/start of conversion mechanism (continued)CLKTLV5718•POST OFFICE BOX 655303 DALLAS, TEXAS 75265tsu(CSL_WRL)th(WRH_CSH)tsu(CSL_RDL)tsu(CSL_RDL)CSWRtd(CSH_CSTARTL)th(RDH_CSH)tct(10 CLKs)ct(sample)t(sample)CSTARTRDtsu(DAV_WRH)th(WRH_DAV)tdis(RDH_DAV)D[0:7]ConfigDataADCADCten(RDL_DAV)ten(RDL_DAV)INTOREOCAuto PowerdownFigure 4. Input Conversion – Hardware CSTART, External ClockSLAS239A – SEPTEMBER 1999 – REVISED FEBRUARY 2000RARALLEL ANALOG-TO-DIGITAL CONVERTER2.7 V to 5.5 V, 1-CHANNEL, 8-BIThttp://oneic.com/internal clockWith CS low and WR low, data is written into the ADC. The sampling begins at the falling edge of CSTART, and conversion begins at the risingedge of CSTART. The internal clock turns on at the rising edge of CSTART. The internal clock is disabled after each conversion.tsu(CSL_WRL)th(WRH_CSH)tsu(CSL_RDL)tsu(CSL_RDL)CStd(CSH_CSTARTL)WRt(STARTOSC)t(sample)th(RDH_CSH)tcCSTART01910INTCLK•POST OFFICE BOX 655303 DALLAS, TEXAS 75265t(STARTOSC)RDtsu(DAV_WRH)th(WRH_DAV)tdis(RDH_DAV)D[0:7]ConfigDataADCADCDataDataten(RDL_DAV)ten(RDL_DAV)INTtcOREOCAuto PowerdownAuto PowerdownFigure 5. Input Conversion – Hardware CSTART, Internal Clock9SLAS239A – SEPTEMBER 1999 – REVISED FEBRUARY 2000PARALLEL ANALOG-TO-DIGITAL CONVERTER2.7 V TO 5.5 V, 1-CHANNEL, 8-BITTLV571http://oneic.com/software START conversionSLAS239A – SEPTEMBER 1999 – REVISED FEBRUARY 2000TLV5712.7 V to 5.5 V, 1-CHANNEL, 8-BITRARALLEL ANALOG-TO-DIGITAL CONVERTER10•POST OFFICE BOX 655303 DALLAS, TEXAS 75265external clockWith CS low and WR low, data is written into the ADC. Sampling begins at the rising edge of WR. The conversion process begins 6 clocksafter sampling begins. At the end of conversion, the INT goes low telling the host that conversion is ready to be read out. EOC B low duringthe conversion. The external clock is active and used as the reference at all times. With this mode, WR and RD should not be applied at therising edge of the clock (see Figure 3).0CLKtsu(CSL_WRL)1567151604515tsu(CSL_RDL)th(RDH_CSH)tsu(CSL_RDL)th(WRH_CSH)CSWRRDt(sample)tsu(DAV_WRH)th(WRH_DAV)D[0:7]ConfigDataADC Datatct(sample)tdis(RDH_DAV)ADC Datatcten(RDL_DAV)INTOREOCten(RDL_DAV)Auto PowerdownFigure 6. Input Conversion – Software Start, External Clock
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