LM9627资料

2022-04-08 来源：星星旅游

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March 2001

LM9627 Color CMOS Image Sensor VGA 30 FPSLM9627 Color CMOS Image Sensor VGA 30 FPS

General Description

The LM9627 is a high performance, low power, third inch VGACMOS Active Pixel Sensor capable of capturing color digital stillor motion images and converting them to a digital data stream.In addition to the active pixel array, an on-chip 12 bit A/D conver-tor, fixed pattern noise elimination circuits and a video gainamplifier is provided. Furthermore, an integrated programmablesmart timing and control circuit allows the user maximum flexibil-ity in adjusting integration time, active window size, gain andframe rate. Various control, timing and power modes are alsoprovided.

Applications

••••••

PC Camera

Digital Still CameraVideo ConferencingSecurity CamerasToys

Machine Vision

Key Specifications

• Array Format• Effective Image Area

Total: 664H x 504VActive: 648H x 488VTotal: 4.98mm x 3.78 mmActive: 4.86 mm x 3.66 mm

1/3“

7.5µm x 7.5µm8,10 & 12 Bit Digital

57dB0.35%

14.5 kLSBs/lux.s7.5 kLSBs/lux.s5.1 kLSBs/lux.s

27%

47% (no micro lens)

Bayer pattern

48 LCC3.3 V90 mW0 to 50oC

Features

••••••••••

Supplied with micro lensesVideo or snapshot operations

Programmable pixel clock, inter-frame and inter-line delays.Programmable partial or full frame integrationProgrammable gain adjustment

Horizontal & vertical sub-sampling (2:1 & 4:2)Windowing

External snapshot trigger & event synchronisation signalsAuto black level compensation

Flexible digital video read-out supporting programmable:-polarity for synchronisation and pixel clock signals

-leading edge adjustment for horizontal synchronizationProgrammable via 2 wire I2C compatible serial interface

• Optical Format• Pixel Size• Video Outputs• Dynamic Range• FPN

• Sensitivity

red green blue• Quantum Efficiency• Fill Factor• Color Mosaic• Package• Single Supply• Power Consumption• Operating Temp

•

•Power on reset & power down mode

System Block Diagram

Storage

lens

LM9627

12bit digital image

Digital ImageProcessor

I2C compatibleevent triggersnapshot

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LM9627Overall Chip Block Diagram

Horizontal Shift Register Bad Pixel Detect & CorrectColumn CDSBlack LevelCompensationDigital VideoFramer d[11:0]pclkhsyncvsyncRow AddressDecoderAPS ArrayPORResetGen

Row AddressGenVerticalTimingAMP12 Bit A/DHorizontal TimingGainControlRegister Bank

I2C Compatible Serial I/FsdasclksadrClock GenController(sequencer)Master TimerPowerControl

mclkextsyncsnapshotirqpdwnFigure 1. Chip Block Diagram

Connection Diagram

vdd_od1vss_od1vdd_od3vss_od3extsyncvdd_pixvsrvddsadrsda6sclksnapshotresetbpdwnvss_digvdd_dighsyncvsyncpclkmclkd0NC78910111213141516171854321 48474645444342414039NCfine_igndfine_ctrloffsetvdd_ana1vss_ana1vref_adcvss_ana2vdd_ana2vss_od2vdd_od2LM962748 PIN LCC31192021222324252627282930NCd1d9d2d3d4d5d6d7d8d10d11Ordering Information

Temperature(0°C ≤ TA ≤ +50°C)

LM9627 CCEA

NS PackageLCC

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LM9627Typical Application CircuitSystem ControlCamera ControlSerial Control Bus16mclk9resetb10pdwn4irq8snapshot48extsync7sclk6sda5sadr3.3V analog37vdd_ana136vss_ana147vdd_od146vss_od1vdd_ana233vss_ana234vdd_od231vss_od2323.3V analog0.1µF0.1µF3.3V digital3.3V digital0.1µF0.1µF3.3V digital44vdd_od345vss_od33vdd_pix2vrlvdd_dig123.3V digital0.1µFvss_dig110.1µF3.3V analogLM9627vsrvdd11.0µF0.1µF3.3V analogvdd_anavdd_ana1.5kΩ35820Ω0.1µFvref_adcfine_i41fine_ctrl391N414822kΩ1%2N390410kΩ1%18194243NCNCNCNChsyncvsyncpclkd10d11d9d8d7d6d5d4d3d2d1d0offset384.7µF1.2kΩ1%gnd40470Ω1%131415302928272625242322212017Digital Video BusFigure 2. Typical Application DiagramScan Read Out Directionpin 1(0,0)vertical scan(0,0)digitalout(0,0)horizontal scanlensCMOS Image SensorFigure 3. Scan directions and position of origin in imaging system Confidential3www.national.com

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LM9627Pin Descriptions

Pin12345

Namevsrvddvrlvdd_pixirqsadr

I/OI0IIOI

TypPAPDD

Description

Analog bidirectional, it should be connect to ground via a 1.0µf capacitor. This pin is the internal charge pump voltage source.

Anti blooming pin. This pin is normally tied to ground. 3.3 volt supply for the pixel array.

Digital output, the interrupt request pin. This pin generates interrupts during snapshot mode.

Digital input with pull down resistor. This pin is used to program different slave addresses for the sensor in an I2C compatible system.

I2C compatible serial interface data bus. The output stage of this pin has an open drain driver.

I2C compatible serial interface clock.

Digital input with pull down resistor used to activate (trigger) a snapshot sequence.Digital input with pull up resistor. When forced to a logic 0 the sensor is reset to its default power up state. The resetb signal is internally synchronized to mclk which must be run-ning for a reset to occur.

Digital input with pull down resistor. When forced to a logic 1 the sensor is put into power down mode.

0 volt power supply for the digital circuits.3.3 volt power supply for the digital circuits.

Digital Bidirectional. This is a dual mode pin. When the sensor’s digital video port is con-figured to be a master, (the default), this pin is an output and is the horizontal synchroni-zation pulse. When the sensor’s digital video port is configured to be a slave, this pin is an input and is the row trigger.

Digital Bidirectional. This is a dual mode pin. When the sensor’s digital video port is con-figured to be a master, (the default), this pin is an output and is the vertical synchroniza-tion pulse. When the sensor’s digital video port is configured to be a slave, this pin is an input and is the frame trigger.Digital output. The pixel clock.

Digital input. The sensor’s master clock input.

Digital output. Bit 0 of the digital video output bus. This output can be put into tri-state mode.

Pin not used, do not connect.Pin not used, do not connect.

Digital output. Bit 1 of the digital video output bus. This output can be put into tri-state mode.

Digital output. Bit 2 of the digital video output bus. This output can be put into tri-state mode.

Digital output. Bit 3 of the digital video output bus. This output can be put into tri-state mode.

Digital output. Bit 4 of the digital video output bus. This output can be put into tri-state mode.

Digital output. Bit 5 of the digital video output bus. This output can be put into tri-state mode.

Digital output. Bit 6 of the digital video output bus. This output can be put into tri-state mode.

678

sdasclksnapshot

IOII

DDD

9resetbID

101112

pdwnvss_digvdd_dig

III

DPP

13hsyncIOD

14vsyncIOD

151617181920

pclkmclkd0NCNCd1

OIO

DDD

21d2OD

2223

d3d4

24d5OD

25d6OD

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LM9627Pin Descriptions (Continued)

Pin2627

Named7d8

I/OOO

TypDD

Description

Digital output. Bit 7 of the digital video output bus. This output can be put into tri-state mode.

Digital output. Bit 8 of the digital video output bus. This output can be put into tri-state mode.

Digital output. Bit 9 of the digital video output bus. This output can be put into tri-state mode.

Digital output. Bit 10 of the digital video output bus. This output can be put into tri-state mode.

Digital output. Bit 11 of the digital video output bus. This output can be put into tri-state mode.

3.3 volt supply for the digital IO buffers.0 volt supply for the digital IO buffers3.3 volt supply for analog circuits.0 volt supply for analog circuits.

A/D reference resistor ladder voltage. See figure 4 for equivalent circuit.0 volt supply for analog circuits.3.3 volt supply for analog circuits.

Analog input used to adjust the offset of the sensor. See figure 4 for equivalent circuit.Analog output used to drive the offset pin. This pin must be tied to ground.

Bias current for the fine offset adjust.Pin not used, do not connect.Pin not used, do not connect.

IIIIO

PPPPD

3.3 volt supply for the sensor.0 volt supply for the sensor.

0 volt supply for the digital IO buffers3.3 volt supply for the digital IO buffers.

Digital output. The external event synchronization signal is used to synchronize external events in snapshot mode.

28d9OD

2930313233343536373839404142434445464748

d10d11vdd_od2vss_od2vdd_ana2vss_ana2vref_adcvss_ana1vdd_ana1offsetfine_ctrlgndfine_iNCNCvdd_od3vss_od3vss_od1vdd_od1extsync

OOIIIIIIIIO

DDPPPPAPPAA

Legend: (I=Input), (O=Output), (IO=Bi-directional), (P=Power), (D=Digital), (A=Analog).adc_vref

800Ω

offset

1KΩ

200Ω

Figure 4. Equivalent Circuits For adc_ref and offset pins

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LM9627Absolute Maximum Ratings (Notes 1 & 2)

Any Positive Supply Voltage6.5VVoltage On Any Input or Output Pin-0.5V to 6.5VInput Current at any pin (Note 3)±25mAESD Susceptibility (Note 5)

Human Body Model2000V

Machine Model200V

Package Input Current (Note 3)±50mAPackage Power Dissipation @ TA(Note 4)2.5WSoldering Temperature Infrared,

10 seconds (Note 6)220°CStorage Temperature-40°C to 125°C

Operating Ratings (Notes 1 & 2)

Operating Temperature Range

All VDD Supply Voltages

Voltage Range on vref_adc pinVoltage Range on offset pin

0°C≤T≤+50°C+3.15V to +3.6V+0.6V to +1.0V+0.04V to +0.4V

DC and logic level specifications

The following specifications apply for all VDD pins= +3.3V. Boldface limits apply for TA = TMIN to TMAX: all other limits TA = 25oC(Note 7)Symbol

Parameter

Conditions

Minnote 9

Typicalnote 8

Maxnote 9

Units

sclk, sda, sadr, Digital Input/Output CharacteristicsVIHVILVOLVhysIleak

Logical “1” Input VoltageLogical “0” Input VoltageLogical “0” Output VoltageHysteresis (SCLK pin only)Input Leakage Current

vdd_od = +3.15V, Iout=3.0mAvdd_od = +3.15VVin=vss_od

0.05*vdd_o

-1

0.7*vdd_od

-0.5

vdd_od+0.50.3*vdd_od

0.5

VVVVmA

mclk, snapshot, pdwn, resetb, hsync, vsync Digital Input CharacteristicsVIHVILIIHIIL

Logical “1” Input VoltageLogical “0” Input VoltageLogical “1” Input CurrentLogical “0” Input Current

vdd_dig = +3.6Vvdd_dig = +3.15VVIH = vdd_digVIL = vss_dig

0.1-1

2.0

0.8

VV mAmA

d0 - d11, pclk, hsync, vsync, extsync, irq, Digital Output CharacteristicsVOHVOLIOZIOS

Logical “1” Output VoltageLogical “0” Output VoltageTRI-STATE Output CurrentOutput Short Circuit Current

vdd_od=3.15V, Iout=-1.6mAvdd_od=3.15V, Iout =-1.6mAVOUT = vss_odVOUT = vdd_od

-0.10.1+/-17

2.2

0.5

V V mAmAmA

Power Supply Characteristics

IAID

Analog Supply CurrentDigital Supply Current

Power down mode, no clock.Operational mode in darkPower down mode, no clock.Operational mode in dark

700193007

mA mA mA mA

Power Dissipation Specifications

The following specifications apply for All VDD pins = +3.3V. Boldface limits apply for TA = TMIN to TMAX: all other limits TA = 25oC.SymbolPdwnPWR

Parameter

Power Down

Average Power Dissipation

Conditions

no clock running

mclk = 48Mhz & sensors default set-tings in dark.

Minnote 9

Typicalnote 8590

Maxnote 9

UnitsmWmW

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LM9627Video Amplifier Specifications

The following specifications apply for all VDD pins= +3.3V. Boldface limits apply for TA = TMIN to TMAX: all other limits TA = 25oC.Symbol

Parameter

Video Amplifier Nominal Gain

Conditions

64 linear steps

Minnote 9

Typicalnote 80-15

Maxnote 9

UnitsdB

AC Electrical Characteristics

The following specifications apply for All VDD pins = +3.3V. Boldface limits apply for TA = TMIN to TMAX: all other limits TA = 25oC.

SymbolFmclkTchTcl

Parameter

Input Clock FrequencyClock High TimeClock Low TimeClock Duty Cycle

Trc, TfcFhclkTresetFRMrate

Note 1:

Clock Input Rise and Fall TimeInternal System Clock Fre-quency

Reset pulse widthFrame Rate

1.01.01

@ CLKmax@ CLKmax@ CLKmax

Conditions

Minnote 912101045/55

14.0

Typicalnote 8

Maxnote 948454555/45

UnitsMHz nsnsmin/maxnsMHzµs fps

Note 2:Note 3:

Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate con-ditions for which the device is functional, but do not guarantee specific performance limits. For guaranteed specificationsand test conditions, see the Electrical Characteristics. The guaranteed specifications apply only for the test conditionslisted. Some performance characteristics may degrade when the device is not operated under the listed test conditions.All voltages are measured with respect to VSS = vss_ana = vss_od = vss_dig = 0V, unless otherwise specified.

When the voltage at any pin exceeds the power supplies (VIN < VSS or VIN > VDD), the current at that pin should be lim-ited to 25mA. The 50mA maximum package input current rating limits the number of pins that can safely exceed the powersupplies with an input current of 25mA.

The absolute maximum junction temperature (TJmax) for this device is 125oC. The maximum allowable power dissipationis dictated by TJmax, the junction-to-ambient thermal resistance (ΘJA), and the ambient temperature (TA), and can be cal-culated using the formula PDMAX = (TJmax - TA)/ΘJA. In the 48-pin LCC, ΘJA is 38.5oC/W, so PDMAX = 2.5W at 25oCand 1.94W at the maximum operating ambient temperature of 50oC. Note that the power dissipation of this device undernormal operation will be well under the PDMAX of the package.

Human body model is 100pF capacitor discharged through a 1.5kΩ resistor. Machine model is 220pF discharged throughZERO Ohms.

See AN450, “Surface Mounting Methods and Their Effect on Product Reliability”, or the section entitled “Surface Mount”found in any post 1986 National Semiconductor Linear Data Book, for other methods of soldering surface mount devices.The analog inputs are protected as shown below. Input voltage magnitude up to 500mV beyond the supply rails will notdamage this device. However, input errors will be generated If the input goes above AV+ and below AGND.

VDD

Note 4:

Note 5:Note 6:Note 7:

Pad

IOP

Internal Circuits

VSS

Note 8:Note 9:

Typical figures are at TJ = 25oC, and represent most likely parametric norms.Test limits are guaranteed to National's AOQL (Average Outgoing Quality Level).

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LM9627CMOS Active Pixel Array Specifications

Parameter

Number of pixels (column, row) Total Active

Array size (x,y Dimensions) Total ActivePixel Pitch

Fill Factor (without micro-lens)

Value 664 x 504 648 x 488 4.98 x 3.78 4.86 x 3.66

7.547

Unitspixelspixelsmmmm

µ%

Image Sensor Specifications

The following specifications apply for All VDD pins = +3.3V, TA = 25oC, Illumination Color Temperature = 2850oK, IR cutoff filter at700nm, mclk = 48MHz, frame rate = 30Hz, vref_adc = 0.6 volt, video gain 0dB.

Parameter

Optical Sensitivity @ A/D output red green blueOptical Sensitivity @ A/D input red green blueDynamic RangeRead Noise

Offset Fixed Pattern Noise

RMS value of pixel FPN in dark as a percentage of full scale.RMS variation of pixel sensitivi-ties as a percentage of the aver-age sensitivity.

Conditions

Min

Typicalnote 114.57.55.12.121.10.75575.30.35

Max

Units

kLSBs/(lux.s)

volt/(lux.s)

dBLSBs%

Sensitivity Fixed Pattern Noise1%

Note 1:

Typical figures are at TJ = 25oC, and represent most likely parametric norms.

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LM9627Sensor Response Curves8.00E+027.00E+02Spectral sensitivity [V/((W/m^2)*s)]6.00E+02green5.00E+02blue4.00E+023.00E+022.00E+021.00E+020.00E+00370red420470520570620670720770820wavelength [nm]Figure 5. Spectral Response CurveA/D output code50004000ADC output code [LSBs]3000greenbluered20001000000.10.20.3Exposure [lux.s]0.40.50.6Figure 6. Linearity Response Curve Confidential9www.national.com

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LM9627Functional Description1.0OVERVIEW0-15dBVideoAMP1.1Light Capture and ConversionThe LM9627 contains a CMOS active pixel array consisting of648 rows by 488 columns. This active region is surrounded by 8columns and 8 rows of optically shielded (black) pixels as shownin Figure7.648 columns, 488 rows color (Bayer pattern) active pixels8 columns, 8 rows black pixels12 Bit A/DAnalog pixel valuesDigital pixel dataFigure 9: Analog Signals Conditioning & Conversion to DigitalThe digital pixel data is further processed to:•remove defects due to bad pixels,•compensate black level, before being framed and presented on the digital output port. (see Figure 10).do[11:0]pclkhsyncvsyncBlack LevelCompensation8 columns, 8 rows black pixelsFigure 10. Digital Pixel Processing.Figure 7: CMOS APS region of the LM9627The color filters are Bayer pattern coded starting at row 8 andcolumn 8. (rows 0 to 7 & columns 0 to 7 are black). The colorcoding is green, red, green, red until the end of row 8, then blue,green, blue, green until the end or row 9 and so on (see Figure7).At the beginning of a given integration time the on-board timingand control circuit will reset every pixel in the array one row at atime as shown in Figure 8. Note that all pixels in the same roware simultaneously reset, but not all pixels in the array. abc0123456789101112131415defghijklmnopqr1.2Program and Control InterfacesThe programming, control and status monitoring of the LM9627is achieved through a two wire I2C compatible serial bus. Inaddition, a slave address pin is provided (see Figure 11).Digital VideoFramer Serial I/FirqextsynsnapshotBad PixelCorrectionsdaRegister BankI2C Compatible sclksadrLine AddressFigure 11. Control Interface to the LM9627.Additional control and status pins: snapshot and external eventsynchronization are provided allowing the latency of the serialcontrol port to be bypassed during single frame capture. Aninterrupt request pin is also available allowing complex snapshotoperations to be controlled via an external micro-processor (seeFigure 12).CDS/Shift RegisterTimingGeneratorAnalog Data OutFigure 8: CMOS APS Row and Column addressing schemeAt the end of the integration time, the timing and control circuitwill address each row and simultaneously transfer the integratedvalue of the pixel to a correlated double sampling circuit andthen to a shift register as shown in Figure 8.Once the correlated double sampled data has been loaded intothe shift register, the timing and control circuit will shift them outone pixel at a time starting with column “a”.The pixel data is then fed into an analog video amplifier, where auser programmed gain is applied (see Figure 9).After gain adjustment the analog value of each pixel is con-verted to a 12 bit digital data as shown in Figure 9. Confidential

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LM9627Functional Description (continued)2.0WINDOWINGThe integrated timing and control circuit allows any size windowin any position within the active region of the array to be read outwith a 1x1 pixel resolution. The window read out is called the“Display Window”.A “Scan Window” must be defined first, by programing the startand end row addresses as shown in Figure 13. Four coordinates(start row address, start column address, end row address &end column address) are programmed to define the size andlocation of the “Display Window” to be read out (see Figure 13).display col display col scan rowend addressstart addressstart address01234567891011121314151617181920Column/Horizontalabcdefghijklmnopqrdisplay row start addressdisplay row end addressscan rowend addressDisplay WindowScan WindowActive Pixel ArrayFigure 13. Windowing3.2Interlaced Readout ModeIn interlaced readout mode, pixels are read out in two fields, anOdd Field followed by an Even Field. The Odd Field, consisting of all even row pairs contained withinthe display window, is read out first. Each pixel in the “Odd Field”is consecutively read out, one pixel at a time, starting with theleft most pixel in the top most row pair.The Even Field, consisting of all odd row pairs contained withinthe display window, is then read out. Each pixel in the “EvenField” is consecutively read out, one pixel at a time, starting withthe left most pixel in the top most row pair.Column/Horizontalabcdefghijklmnopqr01458912131617Odd FieldColumn/Horizontalabcdefghijklmnopqr2367101114151819Notes:•The “Display Window” must always be defined within the “Scan Window”.•A “Display Window” can only be read out in the progressive scan mode.•By default the “Display Window” is the complete array.2.1Programming the scan windowTwo registers (SROWS & SROWE) are provided to program thesize of the scan window. The start and end row address of thescan window is given by:scan row start address = (2* SwStartRow) + SwLsb scan row end address = (2* SwEndRow) + 1 + SwLsb Where:SwStartRow is the contents of the Scan Window start row register (SROWS)SwEndROWis the contents of the Scan Window end row reg-ister (SROWE)SwLsbis bit 6 of the Display Window LSB register (DWLSB)2.2Programming the display windowFive register (DROWS, DROWE, DCOLS, DCOLE and DWLSB)are provided to program the display window as described in theregister section of this datasheet.Row/Vertical11

Row/Vertical3.0READ OUT MODES3.1Progressive Scan Readout ModeIn progressive scan readout mode, every pixel in every row inthe display window is consecutively read out, one pixel at a time,starting with the left most pixel in the top most row. Hence, forthe example shown in Figure 14, the read out order will bea0,b0,...,r0 then a1,b1,...,r1 and so on until pixel r20 is read out. Confidential

Even FieldFigure 15: Interlace Read Out ModeHence, for the example shown in Figure 15, the display windowis broken up into two fields, as shown in Figure 15. Pixelsa0,b0,...,r0 and a1,b1,...,r1 are readout first and so on until pix-els a17,b17,...r17 in the even field are read out. The even fieldread out is followed by pixels in the odd field, a2,b2,...,r2 thena3,b3,...,r3 until pixels a19,b19,...,r19Row/VerticalFigure 14: Progressive Scan Read Out Modewww.national.com

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LM9627Functional Description (continued)

4.0

SUBSAMPLING MODES

4.24:2 Sub-Sampling

The timing and control circuit can be programmed to sub-sam-ple pixels in the display window vertically, horizontally or both,with an aspect ratio of 4:2 as illustrated in Figure17

Column/Horizontalabcdefghijklmnopqr014.12:1 Sub-Sampling

The timing and control circuit can be programmed to sub-sam-ple pixels in the display window vertically, horizontally or both,with an aspect ratio of 2:1 as illustrated in Figure16.

Column/Horizontalabcdefghijklmnopqr0123456789a) Horizontal Sub-Sampling Column/Horizontalabcdefghijklmnopqr0123456789b) Vertical Sub-Sampling Column/Horizontalabcdefghijkl0123456789c) Horizontal & Vertical Sub-Sampling Green PixelNot Read Out

Figure 16: Example of 2:1 Sub-sampling

Red Pixel

Blue Pixel

Row/VerticalRow/Vertical23456789a) Horizontal Sub-sampling Column/Horizontalabcdefghijklmnopqr0123456789b) Vertical Sub-sampling Column/Horizontalabcdefghijklmnopqr0123456789c) Horizontal & Vertical Sub-sampling Green PixelNot Read Out

Figure 17: Example 4:2 Sub-sampling

Red Pixel

Blue Pixel

Row/VerticallnopqrRow/Vertical12

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LM9627Functional Description (continued)5.0SNAPSHOT MODEThe LM9627 is capable of capturing a single frame of an imageunder hardware or software control, with or without the aid of anexternal shutter. Two registers, SNAPSHOTMODE0 &SNAPSHOTMODE1, are provided to program, monitor and con-trol all snapshot sequences.5.1Software Controlled SnapshotsThe snapshot mode events can be software controlled by writingto and reading from the snapshot mode registers over the I2Ccompatible interface. 5.2Hardware Controlled SnapshotsTwo dedicated pins are provided on the LM9627, snapshot &extsync, allowing the snapshot mode events to be controlled byhardware. The snapshot pin must be enabled by writing to theSnapEnable bit of the MCFG0 register.5.3Auto Snapshot ModeIn auto snapshot mode (see figure 20), upon the receipt of asnapshot or FTriggerNow trigger signal, the integrated timing andcontrol circuit will set the FTriggerEN bit and generate an inter-nal TRIGGER signal (see figure 19), thus resetting the array onerow at a time. At end of the reset cycle the timing and control cir-cuit will signal the shutter to open via extsync pin or FtSync bit.At the end of the programmed integration time the shutter will besignalled to close, and the pixel read-out will commence asshown in figure 18a. At the end of the read-out sequence theFTriggerEN will be automatically reset and the sensor will returnto video capture mode as shown in figure 20. If an external shutter is not available then at least two framesneed to be taken so that the pixels can be integrated over oneframe as shown in Figure 18b.To use auto snapshot mode the SsEngage bit of theSNAPSHOTMODE1 register must be set to zero. Array reset, CaptureDataprogrammable 1 to 4 frames imageread-outsnapshot or FTriggerNownote 1note 2note 3irqFTriggerEnextsync or FtSyncFtBusyStart Snapshot SequenceStart of Array Reset Frames Open ShutterClose shutter & start read-outRead-out completea) With External ShutterArray reset, CaptureDataprogrammable 1 to 4 frames imageread-outsnapshot or FTriggerNownote 1note 2note 3irqFTriggerEnextsync or FtSyncFtBusyStart Snapshot sequenceStart of Array Reset Frames Integration StartStart Read-outRead-out Completeb) Without External ShutterNote 1:Note 2:Note 3:This wave form shows the snapshot pin programmed to the default pulse mode.The irq pulse is taken low when the snapshot trigger interrupt flag (SsTrigFlag) in the snapshot mode1 (SNAPMODE1) register is read.The irq pulse is taken low when the snapshot trigger interrupt flag (SsRdFlag) in the snapshot mode1 (SNAPMODE1) register is read.Bold external pinsitalic register bitsFigure 18. Snapshot Mode Confidential13www.national.com

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LM9627Functional Description (continued)

snapshotSnapShotPolSnapEnableFTriggerNow

Figure 19. Snapshot Trigger Generation Logic

c: SsRdFlag && (SnapshotMod || (SnapshotMod && TRIGGER)) TRIGGER

VIDEO

c:TRIGGER==1

VIDEO

c: SnapshotMod || (SnapshotMod && TRIGGER) IRQ

a:SsTrigFlag=1

c:TRIGGER==1

c:FTriggerEn==1

SNAP

a:FTriggerEn=1

SNAP

PREVIEW

a:FTriggerEn=0

PREVIEW

a: SsRdFlag = 1a: FtTriggerEn = 0

Figure 20. Auto Snapshot Mode State Diagram

5.4CPU Snapshot Mode

In CPU snapshot mode, the FTriggerEN is not set automaticallyand an Interrupt generator can be enabled.

Hence, upon the receipt of a snapshot or FTriggerNow triggersignal, the integrated timing and control circuit will generate aninternal TRIGGER signal as shown in figure 19 and then wait inthe IRQ state for the FTriggerEN bit to be manually set as shownin figure 21.

Once the FtriggerEn bit is set the integrated timing and controlcircuit will start resetting the array one row at a time. At end ofthe reset cycle the timing and control circuit will signal the shut-ter to open via extsync pin or FtSync bit. At the end of the pro-grammed integration time the shutter will be signalled to close,and the pixel read-out will commence as shown in figure 18a. Atthe end of the read-out sequence the FTriggerEN will be auto-matically disabled and the sensor will return to video capturemode as shown in figure 20.

If an external shutter is not available then at least two framesneed to be taken so that the pixels can be integrated over oneframe as shown in Figure 18b.

To use CPU snapshot mode the SsEngage bit of theSNAPSHOTMODE1 register must be set to one.

An interrupt generator can be enabled in CPU snapshot modeby setting the SnapIntEn bit of SNAPSHOTMODE1 register. Aninterrupt will be generated on the external interrupt pin, irq,when a snapshot sequence is triggered (TRIGGER=1) or whenthe array readout is complete at the end of the snapshotsequence as shown figure 21. Confidential

When an interrupt is generated by a TRIGGER event, theSsTrigFlag bit in the SNAPSHOTMODE1 register is set. Simi-larly when an interrupt is generated at the completion of a read-out the SsRdFlag in the SNAPSHOTMODE1 register is set.The polarity of the irq pin can be programmed. The interrupt canonly be cleared by reading SsTrigFlag and the SsRdFlag asshown in figure 22.

SsTrigFlagSsRdFlagSnapIntEn

IrqPol

Figure 22. Interrupt Request Generation Logic

5.5Pulse & Level Trigger Mode

The snapshot pin can be programmed to operate in pulse trig-ger mode where one snapshot sequence is executed per activepulse or in level trigger mode where by snapshot sequences arerepeated as long as the level on the snapshot pin is held active.(see figures 20 and 21).

Pulse and level trigger modes can be set by programming theSnapshotMod bit in the SNAPSHOTMODE0 register.

irq

Figure 21. CPU Snapshot Mode State Diagram

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LM9627Functional Description (continued)6.0CLOCK GENERATION MODULEThe number of rows in a scan window is given by:SWNrows = (RADend - RADstart) + 1 Where:RADend RADstartThe LM9627 contains a clock generation module that will createtwo clocks as follows:Hclk,the horizontal clock. This is an internal system clock and can be programmed to be the input clock (mclk) or mclk divided by any number between 1 and 255.CLKpixelthe pixel clock. This is the external pixel clock that appears at the digital video port. It can be Hclk or Hclk divided by 2. This clock cannot be programed.is the end row address of the defined scan win-dow. (See section 2.1)is the start row address of the defined scan win-dow. (Scan section 2.1).The number of Hclk clocks required to process a full frame isgiven by:FNHclk = [(Mfactor * SWNrows) + Fdelay] * RNHclk Where:Mfactor7.0FRAME RATE PROGRAMINGA frame is defined as the time it takes to reset every pixel in thearray, integrate the incident light, convert it to digital data andpresent it on the digital video port. This is not a concurrent pro-cess and is characterized in a series of events each needing acertain amount of time as shown in Figure 23.Startis a Mode Factor which must be applied. It is dependent on the selected mode of operation as shown in the table below:Progressive Scan10.5Row address = 0Sub-sampling or InterlaceRow delay timeSWNrows is the Number of Rows in Selected Scan Win-dow. Fdelay a programmable value between 0 & 4097 repre-senting the Inter Frame Delay in multiples of RNHclk. This parameter allows the frame time to be extended. (See the Frame Delay High and Frame Delay Low registers).The frame rate is given by:Frame Rate = Hclk FNHclkTransfer all pixels to CDSRow TimeReset all pixels in rowShift all pixels out of rowRow address + 1Yes7.2Partial Frame IntegrationIn some cases it is desirable to reduce the time during which thepixels in the array are allowed to integrate incident light withoutchanging the frame rate.NoThis is known as Partial Fame Integration and can be achievedby resetting pixels in a given row ahead of the row beingselected for readout as shown in Figure 24. The number of Hclkclocks required to process a partial frame is given by:FPHclk = RNHclk * Itime Where:RNHclkItimeis the number of Hclk clock cycles required to process & shift out one row of pixels.is the number of rows ahead of the current row Last row?Figure 23. Frame Readout Flow Diagram7.1Full Frame IntegrationFull frame integration is when each pixel in the array integrateslight incident on it for the duration of a frame (see Figure 24).The number of Hclk clock cycles required to process & shift outone row of pixels is given by:RNHclk = Ropcycle + Rdelay Where:Ropcycle is a fixed integer value of 780 representing the Row Operation Cycle Time in multiples of Hclk clock cycles. It is the time required to carry out all fixed row operations outlined in Figure 23.Rdelay a programmable value between 0 & 2047 repre-senting the Row Delay Time in multiples of Hclk. This parameter allows the Row Operation Cycle time to be extended. (See the Row Delay High and Row Delay Low registers). Confidential

to be reset. (See the Integration Time High and Low registers).The Integration time is subject to the following limits:ModeProgressive ScanInterlaceSub-SampledLimitItime <= SWNrows + Fdelay Itime <= SWNrows + 2*Fdelay Itime <= SWNrows + 0.5*Fdelay15www.national.com

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LM9627Functional Description (continued)Full Integration TimePartial Integration TimeRow nFrame DelayRow 0Row 1Row 2Row xRow x+∆Row nFrameDelayRow 0Programmable Row DelayRow CDS, Reset Row x & ShiftFull Frame integrationProgrammable Row DelayRow CDS, Reset Row x+∆ & ShiftPartial Frame Integration Frame NFigure 24. Partial and Full Frame Integration7.3Frame Rate Programming GuideThe table bellow can be used as a guide for programming the sensor. Note that it is assumed that the sensor is being driven with a48MHz clock. All programmed values are given in decimal.registeraddressfps30157.53.752512.56.253.12554321vclkgen05hex 4444455445566rdelayh15hex[10:8]0003000020003rdelayl16hex[7:0]000121720015625500200241fdelayh17hex[11:8]026601514410141315fdelayl18hex[7:0]9401212022618814231214248126srows0Bhex[8:1]0000000000000srowe0Chex[8:1]251251251251251251251251251251251251251dwlsb12hex 50505050505050505050505050 Confidential16www.national.com

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LM9627Functional Description (continued)

8.0

SIGNAL PROCESSING

10.0ANALOG GAIN ADJUSTMENT

The integrated analog programmable gain amplifier is capableof applying a linear gain 1X to 5.6X in 64 linear steps. This canbe programmed using the VGAIN register as shown in the tablebelow:

VidGain

8.1Bad Pixel Detection & Correction

The LM9627 has a built-in bad pixel detection and correctionblock that operates on the fly. This block can be switched off bythe user.

8.2Black Level Compensation

In addition to the programmable gain the LM9627 has a built inblack level compensation block as illustrated in Figure 25. Thisblock can be switched off.

only enabled for black pixelsinput signalcompensated output*aDecCode

0123456789101112131415161718

Hex Code

000102030405060708090A0B0C0D0E0F101112131415161718191A1B1C1D1E1F

GainAmpValue

11.071.151.221.291.371.441.511.581.661.731.81.881.952.022.12.172.242.312.392.462.532.612.682.752.832.92.973.043.123.193.26

VidGainVidGain

DecCode

3233343536373839404142434445464748495051525354555657585960616263

Hex Code

202122232425262728292A2B2C2D2E2F303132333435363738393A3B3C3D3E3F

GainAmpValue3.343.413.483.563.633.73.773.853.923.994.074.144.214.294.364.434.54.584.654.724.84.874.945.025.095.165.235.315.385.455.535.6

*(1-a)+Σ+z-1-Σ+Figure 25. Digital Black Level Compensation.

The black level compensation block will subtract the averagesignal level of the black pixels around the array from the digitalvideo output to compensate for the temperature and integrationtime dependent dark signal level of the pixels. The exponentialaveraging circuit shown in figure 25 only operates on the leastsignificant 8 bits of the video data.

9.0POWER MANAGMENT

9.1Power Up and Down

The LM9627 is equipped with an on-board power managementsystem allowing the analog and digital circuitry to be switchedoff (power down) and on (power up) at any time.

The sensor can be put into power down mode by asserting alogic one on the “pdwn” pin or by writing to the power down bit in

the main configuration register via the IC compatible serialinterface.

To power up the sensor a logic zero can be asserted on the“pdwn” pin or write to the power down bit in the main configura-tion register via the I2C compatible serial interface.

It will take a few milli seconds for all the circuits to power up. Thepower management register contains a bit indicating when thesensor is ready for use. During this time the sensor cannot beused for capturing images. A status bit in the power manage-ment register will indicate when the sensor is ready for use.9.2Advanced Power Features

In addition to the power up/power down features of the sensor,sections of the analog video processing chain can be powereddown and re-routed during normal operation. This flexibilityallows power dissipation to be traded of with signal gain asshown in the table below:

PGA Amponoff

Power Saving0mW10mW

19202122232425262728293031

Figure 26. Power Control

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LM9627Functional Description (continued)

11.0OFFSET ADJUSTMENT

For maximum image quality over a wide range of light conditionsit is necessary to set an appropriate offset voltage before usingthe sensor to capture images. This offset voltage must beapplied to the offset pin (38) of the sensor, and is used to adjustthe analogue video signal being fed to the internal A/D.

The level of the offset voltage determines the black level of theimage and has a direct impact on the image quality. Too high anoffset results in a white washed or hazy looking image, while toolow of an offset results in a dark image with low contrast eventhough the light conditions are good.

A fine offset adjustment should be applied to each part by pro-gramming the offset voltage via the I2C compatible serial inter-face. To program an offset voltage the following procedureshould be followed:

The sensor’s offset, fine_i & fine_ctrl pins should be connectedas shown in figure 2.

The following procedure should be followed to calibrate the off-set

•Disable the black level compensation block by writing a logic 1 to bit 4 of the Main Configuration Register 0 (MCFG0: address 02Hex).

•The offset can be adjusted by writing to the Offset Compen-sation Registers (OCR: addresses 1F, 22 & 25 hex). Writing 00hex will give the largest voltage, while writing FF hex will give the smallest value.

•Run the following binary search algorithm•For n=7 to 0 step -1•{

Set bit n in the OCR registers (addresses 1F, 22 & 25 Hex) to a logic one by writing over the I2C compatible interface.

Read a full frame and calculate the average black level (BLaverage) of the first and last 5 black pixels in the every row of the array

If (BLaverage < 100) then Reset bit n in the OCR registers (addresses 1F, 22 &

25 Hex) to 0else

Keep bit n set to one.}

•Enable the black level compensation block (if desired) by writ-ing a logic 0 to bit 4 of the Main Configuration Register 0 (MCFG0: address 02Hex).

12.0 OFFSET & GAIN

The fine offset adjustment and calibration method described insection 11.0 will ensure that the sensor’s black level is optimizedfor a fixed analog gain setting. However, when the analog gain ischanged substantially, the black level of the sensor will shiftresulting in a white washed image.

To stop this effect from occurring, the black level needs to be re-calibrated. This can be done as part of the contrast adjustmentwhich is carried out by most digital image processors. If this isnot possible then the following method can be used.

The relationship between the gain and the offset can bedescribed with the following equation.

Offset(G) = Offset(0) + C * G0.4

is the offset that needs to be programmed in the OCR1, OCR2 & OCR3 registers to ensure the correct black level setting for an analog gain setting of G.

Offset(0)is the offset that needs to be programmed in

the OCR1, OCR2 & OCR3 registers to ensure the correct black level setting for unity analog gain, (G=0).

Cis a constant and will vary from sensor to sen-sor Gis the value programmed in the VGAIN regis-ter of the sensor which determines the sen-sor’s analog gain.

The following procedure should be used to calculate the value ofC:

Use the calibration procedure described in section 11.0 to deter-mine the offset at unity gain, offset(0). Note the VGAIN registershould be set to 0.

Set the sensor’s analog gain register (VGAIN) to its max setting,31, and repeat the calibration procedure described in section11.0. This will allow the offset at full gain, 31, that needs to beprogrammed in the OCR1, OCR2 & OCR3 registers to ensurethe correct black level setting to be determined.

The value of C for a particular sensor can be calculated usingthe following formula:

C =

Offset(31) - Offset(0)

where:

Offset(G)

3.95

Once the value of C has been calculated, offset values for differ-ent gain settings can be calculated using equation 1. It is recom-mended that a two decimal point accuracy for C is maintained.

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LM9627Functional Description (continued)13.0SERIAL BUSThe serial bus interface consists of the sda (serial data), sclk(serial clock) and sadr (device address select) pins. TheLM9627 can operate only as a slave. The sclk pin is an input, it only and controls the serial interface,all other clock functions within LM9627 use the master clock pin,mclk.13.1Start/Stop ConditionsThe serial bus will recognize a logic 1 to logic 0 transition on thesda pin while the sclk pin is at logic 1 as the start condition. Alogic 0 to logic 1 transition on the sda pin while the sclk pin is atlogic 1 is interrupted as the stop condition as shown in Figure27.sda13.4Data ValidThe master must ensure that data is stable during the logic 1state of the sclk pin. All transitions on the sda pin can only occurwhen the logic level on the sclk pin is “0” as shown in Figure 29.sdasclkdata linestable;data validchangeof dataalloweddata linestable;data validFigure 29. Data Validity13.5Byte FormatEvery byte consists of 8 bits. Each byte transferred on the busmust be followed by an Acknowledge. The most significant bit ofthe byte is should always be transmitted first. See Figure 30.13.6Write OperationA write operation is initiated by the master with a Start Condition followed by the sensor’s Device Address and Write bit. When the master receives an Acknowledge from the sensor it can transmit 8 bit internal register address. The sensor will respond with a second Acknowledge signaling the master to transmit 8 write data bits. A third Acknowledge is issued by the sensor when the data has been successfully received.The write operation is completed when the master asserts a Stop Condition or a second Start Condition. See Figure 31.13.7Read OperationA read operation is initiated by the master with a Start Condition followed by the sensor’s Device Address and Write bit. When the master receives an Acknowledge from the sensor it can transmit the internal Register Address byte. The sensor will respond with a second Acknowledge. The master must then issue a new Start Condition followed by the sensor’s Device Address and read bit. The sensor will respond with an Acknowl-edged followed by the Read Data byte. The read operation is completed when the master asserts a Not Acknowledge followed by Stop Condition or a second Start Con-dition. See Figure 32. sclkSstart conditionPstop conditionFigure 27. Start/Stop Conditions13.2Device AddressThe serial bus Device Address of the LM9627 is set to 1010101when sadr is tied low and 0110011 when sadr is tied high. Thevalue for sadr is set at power up. 13.3AcknowledgmentThe LM9627 will hold the value of the sda pin to a logic 0 duringthe logic 1 state of the Acknowledge clock pulse on sclk asshown in Figure 28.sdafrom mastersdafrom sensor sclkSSTARTMSBACKACK1278Clock pulsefor ACK9Figure 28. AcknowledgesdaMSBack signalfrom receiverbyte completeack signalfrom receiversclk1SSTART278ACKclock line9128ACK9 held lowPFigure 30. Serial Bus Byte FormatSDeviceAddressWARegister AddressAData ByteAPbold sensor actionFigure 31. Serial Bus Write OperationSDeviceAddressWARegisterAddressASDevice AddressRAData Byte_APbold sensor actionFigure 32. Serial Bus Read Operation Confidential

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LM9627Functional Description (continued)14.0DIGITAL VIDEO PORTThe captured image is placed onto a flexible 12-bit digital port asshown in Figure 10. The digital video port consists of a program-mable 12-bit digital Data Out Bus (d[11:0]) and three program-mable synchronisation signals (hsync, vsync, pclk).By default the synchronisation signals are configured to operatein “master” mode. They can be programed to operate in “slave”mode.The following sections are a detailed description of the timingand programming modes of digital video port.Pixel data is output on a 12-bit digital video bus. This bus can betri-stated by asserting the TriState bit in the VIDEOMODE1 reg-ister.14.1Digital Video Data Out Bus (d[11:0])A programmable matrix switch is provided to map the output ofthe internal pixel framer to the pins of the digital video bus asillustrated in Figure 33.Internal Pixel Framer Output Register11109876543210LM9627This feature allows a programmable digital gain to be imple-mented when connecting the sensor to 8 or 10 bit digital videoprocessing systems as illustrated in Figure 34. The unused bitson the digital video bus can be optionally tri-stated.d11d10d9d8d7d6d5d4d3d2d1d0d9d8d7d6d5d4d3d2d1d0LM962710 bitDigitalImageProcessora) LM9627 Connected to a 10 bit Digital Image Processors d11d10d9d8d7d6d5d4d3d2d1d0d7d6d5d4d3d2d1d08 bitDigitalImageProcessord11 d10 d9 d8d7 d6 d5 d4 d3 d2 d1 d0 a) MSB Bit 11, Switch Mode (default)Internal Pixel Framer Output Register11109876543210b) LM9627 Connected to a 8 bit Digital Image ProcessorsFigure 34. Example of connection to 10/8 bit systemsSynchronisation Signals in Master ModeBy default the sensor’s digital video port’s synchronisation sig-nals are configured to operate in master mode. In master modethe integrated timing and control block controls the flow of dataonto the 12-bit digital port, three synchronisation outputs areprovided: pclkis the pixel clock output pin.hsyncis the horizontal synchronisation output signal.vsyncis the vertical synchronisation output signal.14.2Pixel Clock Output Pin (pclk) (Master Mode)The pixel clock output pin, pclk, is provided to act as a synchro-nisation reference for the pixel data appearing at the digitalvideo out bus pins d[11:0]. This pin can be programmed to oper-ate in two modes:•In free running mode the pixel clock output pin, pclk, is always running with a fixed period. Pixel data appearing on the digital video bus d[11:0] are synchronized to a specified active edge of the clock as shown in Figure 35.pclkd[11:0]a) pclk active edge negative d11 d10 d9 d8d7 d6 d5 d4 d3 d2 d1 d0b) MSB Bit 10, Switch ModeInternal Pixel Framer Output Register11109876543210d11 d10 d9 d8d7 d6 d5 d4 d3 d2 d1 d0c) MSB bit 9, Switch ModeInternal Pixel Framer Output Register11109876543210pclkd[11:0]b) pclk active edge positive (default) invalid pixel dataFigure 35. pclk in Free Running Mode•In data ready mode, the pixel clock output pin (pclk) will pro-duce a pulse with a specified level every time valid pixel data appears on the digital video bus d[11:0] as shown in Figure 36.d11 d10 d9 d8d7 d6 d5 d4 d3 d2 d1 d0d) MSB bit 8, Switch ModeFigure 33. Digital Video Bus Switching Modes Confidential

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LM9627Functional Description (continued)pclkd[11:0]a) pclk active edge negative pclkd[11:0]b) pclk active edge positive invalid pixel dataFigure 36. pclk in Data Ready ModeBy default the pixel clock is a free running active low (pixel datachanges on the positive edge of the clock) with a period equal tothe internal hclk. The active edge of the clock can be pro-grammed such that pixel data changes on the positive or nega-tive edge of the clock.14.3Horizontal Synchronisation Output Pin (hsync)The horizontal synchronisation output pin, hsync, is used as anindicator for row data. The hsync output pin can be programmedto operate in two modes as follows:•Level mode should be used when the pixel clock, pclk, is pro-grammed to operate in free running mode. In level mode the hsync output pin will go to the specified level (high or low) at the start of each row and remain at that level until the last pixel of that row is read out on d[11:0] as shown in Figure 37. The hsync level is always synchronized to the active edge of pclk.pclkd[11:0]hsyncRow nRow n+114.4Vertical/Horizontal Synchronisation Pin (vsync)The vertical synchronisation output pin, vsync, is used as anindicator for pixel data within a frame. The vsync output pin canbe programmed to operate in two modes as follows:•Level mode should be used when the pixel clock, pclk, is pro-grammed to operate in free running mode. In level mode the vsync output pin will go to the specified level (high or low) at the start of each frame and remain at that level until the last pixel of that row in the frame is placed on d[11:0] as shown in Figure 39. The hsync level is always synchronized to the active edge of pclk.pclkd[11:0]vsyncFrame n+1Frame na) vsync programmed to be active high pclkd[11:0]vsyncFrame nFrame n+1b) vsync programmed to be active low invalid pixel dataFigure 39. vsync in Level Mode•Pulse mode should be used when the pixel clock, pclk, is pro-grammed to operate in data ready mode. In pulse mode the vsync output pin will produce a pulse at the end of each frame. The width of the pulse will be a minimum of four hclk cycles and its polarity can be programmed as shown in Figure 40. The vsync level is always synchronized to the active edge of pclk. pclkd[11:0]vsyncFrame n+1Frame na) vsync programmed to be active higha) hsync programmed to be active high (default) pclkd[11:0]Row n+1Row nb) hsync programmed to be active low invalid pixel dataFigure 37. hsync in Level Mode•Pulse mode should be used when the pixel clock, pclk, is pro-grammed to operate in data ready mode. In pulse mode the hsync output pin will produce a pulse at the end of each row. The width of the pulse will be a minimum of four pclk cycles and its polarity can be programmed as shown in Figure 38. The hsync level is always synchronized to the active edge of pclkpclkd[11:0]hsyncpclkd[11:0]hsyncRow nRow n+1b) hsync programmed to be active lowinvalid pixel dataFigure 38. hsync in Pulse ModeBy default the first pixel data at the beginning of each row isplaced on the digital video bus as soon as hsync is activated. Itis possible to program up to 15 dummy pixels to be readout atthe beginning of each row before the real pixel data is readout.This feature is supported for both level and pulse mode. Confidential

Row n+1Row na) hsync programmed to be active highhsyncpclkd[11:0]vsyncFrame nFrame n+1b) vsync programmed to be active low (default)invalid pixel dataFigure 40. vsync in pulse mode14.5Odd/Even ModeIn odd/even mode the vsync signal is used to indicate whenpixel data from an odd and even field is being placed on the dig-ital video bus d[11:0]. The polarity of vsync can still be pro-grammed in this mode as shown in Figure 41 pclkd[11:0]vsyncOdd FieldEven Fielda) vsync programmed to be active high (default) pclkd[11:0]vsyncOdd FieldEven Fieldb) vsync programmed to be active low invalid pixel dataFigure 41. vsync in odd/even Mode21

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LM9627Functional Description (continued)

pclkvsynchsyncd[11:0]c0c1c2c3c4c5c6c7c8c9c0c1c2c3c4c5c6c7c8c9c0c1c2c3c4c5c6c7c8c9c0c1c2c3c4c5c6c7c8c9row1frame 1row 2row 1frame 2row 2Programmable hsync to 1st valid pixel delayProgrammable inter-frame delay Programmable row delayFigure 42. Example of Digital Video Port Timing in Progressive Scan Mode

pclkvsynchsyncd[11:0]c0c1c2c3c4c5c6c7c8c9c0c1c2c3c4c5c6c7c8c9c0c1c2c3c4c5c6c7c8c9c0c1c2c3c4c5c6c7c8c9row1 Odd Fieldrow 3 row 2 Even Fieldrow 4 Programmable hsync to 1st valid pixel delayProgrammable inter-frame delay Programmable row delay Figure 43. Example of Digital Video Port Timing in Interlaced Mode

pclkvsynchysyncd[11:0]c0c2c4c6c8c0c2c4c6c8c0c2c4c6c8c0c2c4c6c8row 1frame 1row 3row 1frame 2row 3Programmable hsync to 1st valid pixel delayProgrammable inter-frame delay Programmable inter-row delay Figure 44. Example of Digital Video Port Timing in 2:1 Sub-sampling Mode

pclkvsynchsyncd[11:0]c0c2c4c6c8c0c2c4c6c8c0c2c4c6c8c0c2c4c5c8row 1frame 1row 2row 1frame 2row 2Programmable hsync to 1st valid pixel delayProgrammable inter-frame delay Programmable inter-row delayFigure 45. Example of Digital Video Port Timing in 4:2 Sub-sampling Mode

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LM9627Functional Description (continued)14.6Synchronisation Signals in Slave ModeThe sensor’s digital video port’s synchronisation signals can beprogrammed to operate in slave mode. In slave mode the inte-grated timing and control block will only start frame and row pro-cessing upon the receipt of triggers from an external source. Only two synchronization signals are used in slave mode as fol-lows:hsyncis the row trigger input signal.vsyncis the frame trigger input signal.Figure 46 shows the LM9627’s digital video port in slave modeconnected to a digital video processor master DVP.d[11:0]hsyncvsyncpclkmclkLM9627MasterClockdin[11:0]RowTrigFrameTrig14.8Frame Trigger Input Pin (vsync)The frame trigger input pin, vsync, is used to reset the rowaddress counter and prepare the array for row processing. Itmust be activated for at least one “mclk” cycle and no more than96 mclk cycles after the activation of hsync as illustrated in Fig-ure 48.The polarity of the active level of the row trigger is programma-ble. By default it is active high.780 clock cycles per line14.7Row Trigger Input Pin (hsync)The row trigger input pin, hsync, is used to trigger the process-ing of a given row. It must be activated for at least two “mclk”cycle. The first pixel data will appear at d[11:0] “Xmclk“periodsafter the assertion of the row trigger, were Xmclk is given by:Xmclk = 124 + DWStAd Where:DWStAdis the value of the display window column start address.The polarity of the active level of the row trigger is programma-ble. By default it is active high.DVPFigure 46. LM9627 in slave mode hsyncpixel 11pixel 12pixel 652d[11:0]642 valid pixelsmclkcount7767777787790123...134135136136137...77477577677777877901mclkFigure 47. hsync slave mode timing diagram for centred display window of 642 pixels780 clock cycles per linehsyncNo more than96 clock cycles vsyncinternal rowcounterline 502line502line503line 0mclkcountmclk7767777787790123...77477577677777877901...77477577677777877901Figure 48. vsync slave mode timing diagram for scan window of 504 rows. Confidential23www.national.com

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LM9627MEMORY MAP

ADDR00h01h02h03h04h05h06h07h08h09h0Ah0Bh0Ch0Dh0Eh0Fh10h11h12h13h14h15h16h17h18h19h1Fh22h25h26h27h28h29h2Ah

DROWSDROWEDCOLSDCOLEDWLSBITIMEHITIMELRDELAYHRDELAYLFDELAYHFDELAYLVGAINOCR1OCR1OCR2BLCOEFFBPTH0HBPTH0LBPTH1HBPTH1L

00hFBh00hA5h32h00h00h00h00h00h00h00h00h00h00h00h00h00h00h00h

REVMCFG0MCFG1PCRVCLKGENVMODE0VMODE1VMODE2SNAPMODE0SNAPMODE1SROWSSROWE

02h00h00h00h04h00h00h00h00h00h00hFBh

Reset Value

Description

Reserved for future use.Revision Register

Main Configuration Register 0Main Configuration Register 1Power Control Register.Video Clock GeneratorVideo Mode 0 RegisterVideo Mode 1 RegisterVideo Mode 2 RegisterSnapshot Mode 0 RegisterSnapshot Mode 1 RegisterScan Window Row Start RegisterScan Window Row End RegisterReserved for future use.

Display Window Row Start RegisterDisplay Window Row End RegisterDisplay Window Column Start RegisterDisplay Window Column End RegisterDisplay Window LSB Register.Integration Time High RegisterIntegration Time Low RegisterRow Delay High RegisterRow Delay Low RegisterFrame Delay High RegisterFrame Delay Low RegisterVideo Gain Register

Offset Compensation Register 1Offset Compensation Register 1Offset Compensation Register 2

Black Level Compensation Coefficient RegisterBad pixel Threshold 0 High RegisterBad pixel Threshold 0 Low RegisterBad pixel Threshold 1 High RegisterBad pixel Threshold 1 Low Register

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LM9627Register Set

The following section describes all available registers in theLM9627 register bank and their function.Register NameMnemonicAddressType

Bit7:0

Device Rev RegisterREV01 Hex

Read Only.

Description

The silicon revision register.

Reset Value

Bit7

Main Configuration 103 HexMCFG1Read/Write00 Hex

Description

Assert when using a mono-chrome sensor. When this bit is at a logic 1, Sub-Sampling is set to 2:1 and every other row is read out during interlace mode. Clear (the default) when using a color sensor. When this bit is at logic 0, sub-sampling is set to 4:2 and every other row pair is read out during interlace mode.Assert to set the sensor to inter-lace readout mode. Clear (the default) to set the sensor to pro-gressive scan read out mode.Assert to enable horizontal sub-sampling. Clear (the default) to disable horizontal sub-sampling.Assert to enable vertical sub-sampling. Clear (the default) to disable vertical sub-sampling.Reserved

SlaveMode

Use to configure the digital

video port’s synchronisation sig-nal to operate in slave mode. By default the digital video’s port’s synchronization signals are con-figured to operate in master mode.Reserved

Power Control Register 104 HexPCR

Read/Write00 Hex

Description

Assert to route the analog videosignal from the output of the CDSto the input of the 12 bit A/D. Clear(the default) to route the signal tothe video gain amplifier.Reserved

PwdnPGA

Assert to power down the pro-grammable video gain amplifier. Clear (the default) to power up the video gain amplifiers.Reserved

PwDnADC

Assert to power down the 12 bit analog to digital convertor. Clear (the default) to power up the 12 bit analog to digital convertor.

Bit SymbolColorMode

Bit SymbolSiRev

Reset ValueBit7

Main Configuration 002 HexMCFG0Read/Write00 Hex

Description

(Read Only Bit)

Indicates that power on initializa-tion is in progress. The sensor isready for use when this bit is atlogic 0.

Assert to power down the sensor.Writing a logic 1 to this register bithas the same effect as taking thepdwn pin high. Clear (the default)this bit to power up the sensor.Assert to enable the bad pixel detection and correction circuit. Clear (the default) to switch it off.Assert to disable the black level compensation circuit. Clear (the default) to switch it on.

Assert to enable the external snapshot pin. Clear (the default) to disable the external snapshot pin.Reserved

ScanMode

Bit SymbolPwrUpBusy

5HSubSamEn

6PwrDown

4VSubSamEn

5BPCorrection

4BlkLComp3SnapEnable

1:0

Bit SymbolByPassGain6:43

2:10

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LM9627Register Set (continued)

Reset Value

Bit7:0

Hclk Generator Register05 HexVCLKGENRead/Write04 Hex.

Description

Use to divide the frequency ofthe sensors master clock input,mclk to generate the internalsensor clock, Hclk.

Program 00 Hex (the default) forHclk to equal mclk or dividemclk by any number between 1and FF Hex.

BitBit SymbolDescription7PixClkModeAssert to set the pclk to “data ready mode”. Clear, the default, to set pclk to “free running mode”.Assert to set the vsync pin to “pulse mode”. Clear (the default) to set the vsync signal to “level mode”.

Assert to force the hsync signal to pulse for a minimum of four pixel clocks at the end of each row. Clear (the default) to force the hsync signal to a level indicating valid data within a row.

Assert to set the active edge of the pixel clock to negative. Clear (the default) to set the active edge of the clock to positive.

Assert to force the vsync signal to generate a logic 0 during a frame readout (Level Mode), or a nega-tive pulse at the end of a frame readout (Pulse Mode). Clear (the default) to force the vsync signal to generate a logic 1 during a frame readout (Level Mode), or a negative pulse at the end of a frame readout (Pulse Mode).

Assert to force the hsync signal to generate a logic 0 during a row readout (Level Mode), or a nega-tive pulse at the end of a row readout (Pulse Mode). Clear (the default) to force the hsync signal to generate a logic 1 during a row readout (Level Mode), or a nega-tive pulse at the end of a readout (Pulse Mode).

Assert to force the vsync pin to act as an odd/even field indicator. Clear (the default) to force the vsync pin to act as a vertical syn-chronization signal.

Assert to tri-state all output signals (data and control) on the digital video port. Clear (default) to enable all signals (data and con-trol) on the digital video port.

Bit SymbolHclkGen

6VsyncMode5HsyncModeRegister NameAddressMnemonicType

Reset Value

Bit7:6

Digital Video Mode 006 HexVMODE0Read/Write00 Hex

Description

Use to program the number of active bits on the digital video bus d[11:0], starting from the MSB (d[11]). Inactive bits are tri-stated.:00

12 bit mode, bits d[11:0] of the digital video bus are active. This is the default.10 bit mode, bits d[11:2] of the digital video bus are active.8 bit mode, bits d[11:4] of the digital video bus are active.Reserved.

4PixClkPolBit SymbolPixDataSel

3VsynPol2HsynPol01

5:4

PixDataMsb

Use to program the routing of the MSB output of the internal video A/D to a bit on the digital video bus. 00011011

A/D [11:0] -> d[11:0]. A/D [10:0] -> d[11:1]A/D [9:0] -> d[11:2]A/D [8:0] -> d[11:3]

1OddEvenEn0TriState3:0Reserved

Reset Value

Bit7:4Digital Video Mode 208 HexVMODE2Read/Write00 Hex

Description

Use to program the leading edge of hsync to the first valid pixel at the beginning of each row. This can be 0-hex to F-hex corre-sponding to 0 - 15 pixel clocks. Default 0.Reserved

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Bit SymbolHsyncAdjust3:0

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LM9627Register Set (continued)

Reset ValueBit7.6

Snapshot Mode Configuration Register 009 Hex

SNAPMODE0Read/Write00 Hex

Description

Program to set the number of frames required before readout during a snapshot with no external shutter, (see Figure 18). By

default these two bits are set to 00 resulting in one frame before readout:0011011

ShutterEn

one frametwo framesthree framesfour frames

SsRdFlag

Reset Value

Bit

Snapshot Mode Configuration Register 10A Hex

SNAPMODE1Read/Write00 Hex.

Description

Assert to enable the snapshot interrupt generator. Clear (the default) to disable the interrupt generator.

(Read Only Bit)

Snapshot trigger interrupt flag.A logic 1 in this bit indicates thatthe generated interrupt on theirq pin is due to a snapshot trig-ger. This bit is cleared whenread.

(Read Only Bit)

Snapshot read done interruptflag. A logic 1 in this bit indicatesthat the generated interrupt onthe irq pin is due to the comple-tion of a snapshot readoutsequence. This bit is clearedwhen read.

Assert to allow a CPU controlled snapshot sequence. In this mode the snapshot trigger will only generate an interrupt to the CPU and the CPU must manu-ally start the snapshot sequence by asserting the FTriggerEn bit of this register.

Clear (the default) engage an automatic snapshot sequence. In auto mode the snapshot

sequence is started as soon as a snapshot trigger is asserted.(Read Only Bit)

The internal synchronisation signal. A logic 1 on this bit indi-cates a synchronization event is required. This bit is functionally equivalent to the external extsync pin.

(Read Only Bit)

The Frame Trigger Busy bit. A logic 1 on this bit indicates that the sensor is busy reading out pixel data as shown in Figure 18.

Assert to start a snapshot sequence. The frame trigger now is functionally equivalent to the external snapshot pin. The default is 0.

Assert to enable a snapshot sequence (see the SsEngage bit of this register). The default is 0.

Bit SymbolSsFrames

Bit SymbolSnapIntEn

6SsTrigFlag

Assert to indicate that an external shutter will be used during snap-shot mode. Clear (the default) to indicate that snapshot mode will be carried out without the aid of an external shutter.

Assert to set the active level of the extsync signal to 0. Clear (the default) to set the active level of the extsync signal to 1.Reserved

SsEngage4ExtSynPol

SnapshotMod

Assert to set the snapshot pin to level mode. In level mode the sen-sor will continually run snapshot sequences as long as the snap-shot pin is held to the active level. Clear (the default) to set the snap-shot signal to pulse mode. In pulse mode the sensor will only carry out one snapshot sequence per pulse applied to the snapshot pin.

Assert to set the snapshot pin to be active on the positive edge. Clear (the default) to set the snap-shot pin to be active on the nega-tive edge.

Assert to set the active level of the irq signal to 0, Clear (the default) to set the active level of the irq signal to 1.

3FtSync

1SnapShotPol

2FtBusy

0IrqPol

1FTriggerNow

0FTriggerEn

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LM9627Register Set (continued)

Reset Value

Bit7:0

Scan Window Row Start Register0B HexSROWSRead/Write00 Hex

Description

Use to program the scan window’sstart row address MSBs. If bit 6 ofregister DWLSB is set to 1 thestart row address is incrementedby 1 else the raw value is used.

Reset Value

Bit7:0

Display Window Column Start Register10 HexDCOLSRead/Write00 Hex

Description

Use to program the display win-dow’s start column addressMSBs. The two LSBs can be pro-grammed using the DWLSB regis-ter.

Bit SymbolSwStartRow

Bit SymbolDwStartCol

Reset Value

Bit7:0

Scan Window Row End Register0C HexSROWERead/WriteFB Hex

Description

Use to program the scan window’send row address MSBs. If bit 6 ofregister DWLSB is set to 1 the endrow address is incremented by 1.else the raw value is used.

Reset Value

Bit7:0

Display Window Column End Register11 HexDCOLERead/WriteA5 Hex

Description

Use to program the scan window’send column address MSBs. Thetwo LSBs can be programmedusing the DWLSB register.

Bit SymbolSwEndRow

Bit SymbolDwEndCol

Bit7:0

Display Window Row Start Register0E HexDROWSRead/Write00 Hex

Description

Use to program the display win-dow’s start row address MSBs.The LSB can be programmedusing the DWLSB register.

Reset Value

Bit76

Display Window LSB register12 HexDWLSBRead/Write32 Hex

Description

Reserved

Bit Symbol

Bit SymbolDwStartRow

SwLsb

Assert to increment the value ofthe scan window start and endrow addresses by 1. Clear (thedefault) to use the raw values.Use to program bit 1 of the displaywindow’s end column address.Default is 1.

Use to program bit 0 of the displaywindow’s end column address.Default is 1.

Use to program bit 1 of the displaywindow’s start column address.Default is 0.

Use to program bit 0 of the displaywindow’s start column address.Default is 0.

Use to program bit 0 of the displaywindow’s end row address.Default is 1.

Use to program bit 0 of the displaywindow’s start row address.Default is 0.

Reset Value

Bit7:0

Display Row End Register0F HexDROWERead/WriteFB Hex

Description

Use to program the scan window’send row address. The LSB can beprogrammed using the DWLSBregister.

5DwCel[1]

4DwCel[0]

Bit SymbolDwEndRow

3DwCSL[1]

2DwCSL [0]

1DwERLsb

0DwSRLsb

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LM9627Register Set (continued)

Reset Value

Bit7:43:0

Itime[11:8]

Integration Time High Register13 HexITIMEHRead/Write00 Hex.

Description

Reserved

Program to set the integrationtime of the array. The value pro-grammed in the register is thenumber of rows ahead of theselected row to be reset.

Reset Value

Bit7:0

Frame Delay Low Register18 HexFDELAYLRead/Write00 Hex

Description

Use to program the LSBs ofthe frame delay.

Bit SymbolBit SymbolFDelay [7:0]

Reset Value

Bit7:0

Integration Time Low Register14 HexITIMEL

Read/Write00 Hex.

Description

Program to set the integrationtime of the array. The value pro-grammed in the register is thenumber of rows ahead of theselected row to be reset.

Reset Value

Bit7:65:0

Video Gain Register19 HexVGAIN

Read/Write00 Hex

Description

Reserved

Bit Symbol

VidGain

Bit SymbolItime[7:0]

Use to program the overall video gain. 00hex corresponds to a gain of 0dB while 3Fhex corresponds to a gain of 15dB. Steps are in lin-ear increments.

Reset Value

Bit7:32:0

Row Delay High Register15 HexRDELAYHRead/Write00 Hex.

Description

Reserved

Reset Value

Bit7:0

Offset Compensation Register 01FHexOCR0

Read/Write00 Hex

Description

This register defines the volt-age level appearing on the offset_ctrl pin.

Bit SymbolOffsetVol

Bit Symbol

Rdelay[10:8]

Use to program the MSBs of the row delay.

Reset Value

Bit7:0

Row Delay Low Register16 HexRDELAYLRead/Write00 Hex

Description

Use to program the LSBs of the row delay.

Reset Value

Bit7:0

Offset Compensation Register 122 HexOCR1

Read/Write00 Hex

Description

This register defines the volt-age level appearing on the offset_ctrl pin.

Bit SymbolOffsetVol

Bit SymbolRdelay[7:0]

Reset Value

Bit7:43:0

Frame Delay High Register17

FDELAYHRead/Write00 Hex

Description

Reserved

Reset Value

Bit7:0

Offset Compensation Register 225 HexOCR2

Read/Write00 Hex

Description

This register defines the volt-age level appearing on the offset_ctrl pin.

Bit SymbolOffsetVol

Bit Symbol

FDelay[11:8]

Use to program the MSBs of theframe delay.

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LM9627Register Set (continued)

Address26 HexMnemonicBLCOEFFTypeRead/WriteReset Value00 Hex

Bit7:0

Bit SymbolAlpha[7:0]

Description

Exponential averaging coeffi-cient for black pixels

Reset Value

Bit7:0

Threshold 0 High Register27 HexBPTH0HRead/Write00 Hex.

Description

Use to program the MSBs ofthe bad pixel correctionthreshold 0.

Bit SymbolBpT0 [11:4]

Reset Value

Bit7:4

Threshold 0 Low Register28 HexBPTH0LRead/Write00 Hex

Description

Use to program the LSBs ofthe bad pixel correctionthreshold 0.Reserved

Threshold 1 High Register29 HexBPTH1HRead/Write00 Hex

Description

Use to program the MSBs ofthe bad pixel correctionthreshold 1.

Bit SymbolBpT0 [3.0]

3:0

Reset Value

Bit7:0

Bit SymbolTHR1[11.4]

Reset Value

Bit7:4

Threshold 1 Low Register2A HexBPTH1LRead/Write00 Hex

Description

Use to program the LSBs ofthe bad pixel correctionthreshold 1.Reserved

Bit SymbolTHR1 [3.0]

3:0

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LM9627Timing Information1.0pclkhsynct1t2DIGITAL VIDEO PORT MASTER MODE TIMINGd[11:0]t3P0P1PnFigure 49. Row Timing Diagrampclkvsynct5t6hsyncR2t2t1R3RnFigure 50. Frame Timingpclkvsynct5t6hsyncFdelayn-2Fdelayn-1FdelaynR0R1t1R2t2Frame (n)RnInter Frame DelayFigure 51. Frame Delay Timing (With Inter Frame Delay).Labelt0Descriptionspclk periodMin74.4nsTyp83.3nsMax1.0µst1hsync low level mode pulse modehsync high level mode pulse modefirst valid pixel data after hsync activevsync low level mode pulse modevsync high level mode pulse modeSee Frame Rate Programming section for more detailsSee Digital Video Port Registers for more details31

(116-HsyncAdjust) *pclk (see note a & b)16 * pclk(664 -HsyncAdjust) *pclk (see note a & b)764 * pclkHsyncAdjust * pclk (see note a & b)116 *pclk (see note a & b)16 * pclk(FNHclk - 116) * pclk (see note a & b)16 * pclkt2t3t5t6Note a:Note b: Confidentialwww.national.com

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LM9627Timing Information (continued)d[11:0]hsyncvsyncpclkt1t2Figure 52. d[11:0], hsync & vsync to Active High pclk Timingd[11:0]hsyncvsyncpclkt3t4Figure 53. d[11:0], hsync & vsync to Active Low pclk TimingThe following specifications apply for all supply pins = +3.3V and CL = 10pF unless otherwise noted. Boldface limits apply for TA =TMIN to TMAX: all other limits TA = 25oC (Note 7)Labelt1t2t3t4DescriptionsRising pclk to Rising hsync, vsync or d[11:0]Rising pclk to Falling hsync, vsync or d[11:0]Falling pclk to rising hsync, vsync or d[11:0]Falling pclk to falling hsync, vsync or d[11:0]MinTyp25ns23ns25ns23nsMax Confidential32www.national.com

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LM9627Timing Information (continued)2.0DIGITAL VIDEO PORT SLAVE MODE TIMINGt3t1hsynctrigger row nt2trigger row n+1d[11:0]P652P653P654P640P1P652P653P654P655mclkRow n-1Row nFigure 54. Slave Mode Row Trigger and Readout Timinghsynctrigger last row in frame nt5vsynctrigger Frame n+1mclkt4Figure 55. Slave Mode d[11:0], hsync & vsync to pclk Timingd[11:0]mclkt6Figure 56. Rising Edge of mclk to Valid Pixel DataThe following specifications apply for all supply pins = +3.0V & CL = 10pF unless otherwise noted. Boldface limits apply for TA =TMIN to TMAX: all other limits TA = 25oC (Note 7)Labelt1t2t3t4t5t6DescriptionsPulse width of row triggerFirst pixel out after rising edge of row triggerMinimum time between row triggers.Max time to assert next frame trigger after last row trigger.Pulse width of Frame triggerTime to valid pixel data after rising edge of mclk2 * mclk44nsMin2 * mclk124 * mclk780 * mclk96 * mclk124 * mclkTypMax Confidential33www.national.com

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LM9627Timing Information (continued)3.0DIGITAL VIDEO PORT SINGLE FRAME CAPTURE (SNAPSHOT MODE) TIMINGt1snapshot or FTriggerNowirqFTriggerEnextsync or FtSyncFtBusyt2t3t4Figure 57. Snapshot Mode Timing With External Shuttert1snapshot or FTriggerNowirqFTriggerEnextsync or FtSyncFtBusyt2t3t4Figure 58. Snapshot Timing Without External ShutterLabelt1t2t3t4Note a:Note b:DescriptionsMinimum Snapshot Trigger Pulse WidthMinimum time from Snapshot Pulse to extsyncArray Integration TimePixel Read OutSee 7.0Frame Rate Programming section for more detailsSee Snapshot Mode for more detailsEquation2 * mclk (see notes a & b)FNHclk (see notes a & b)FNHclk (see notes a & b)FNHclk (see notes a & b) Confidential34www.national.com

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LM9627Timing Information (continued)4.0SERIAL BUS TIMINGSrSrPtfDAtfDASDAtSU;STAtHD;DATtHD;STAtSU;DATtSU;STOSCLKtrCLtrCLtrCL1trCL1(1)= Rp resistor pull-up= MCS current source pull-uptHIGHtLOWtLOWtHIGH(1) Rising edge of the first SCLK pulse after an acknowledge bit.Figure 59. I2C Compatible Serial Bus Timing.The following specifications apply for all supply pins = +3.3V, CL = 10pF, and sclk = 400KHz unless otherwise noted. Boldface limitsapply for TA = TMIN to TMAX: all other limits TA = 25oC (Note 7)PARAMETERsclk clock frequencySet-up time (repeated) START conditionHold time (repeated) START conditionLOW period of the sclk clockHIGH period of the sclk clockData set-up timeData hold timeSet-up time for STOP conditionCapacitive load for sda and sclk linesSYMBOLfSCLHtSU;STAtHD;STAtLOWtHIGHtSU;DATtHD;DATtSU;STOCb MIN00.60.61.30.618000.6400MAX400-----0.9UNITKHzµSµSµSµSnSµSµSpF Confidential35www.national.com

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LM9627Array Mechanical Information.440 +/-.005 TYP [11.18 +/- 0.12] .040 +/-.003 TYP [1.02 +/- 0.07] .060 +.010 TYP -.005[1.52 + 0.25][- 0.12] 743.085 +/-.010 [2.16 +/- 0.25] 481642distance from pixel (die surface) to top surface of glass lid= 0.894 mm R.0075 +/-.0050[0.191+/- 0.127]TYP .020 +/-.003 [0.51 +/- 0.07] TYP 0.328[8.325]Note 3 311830.040 +/-.007 TYP [1.02 +/- 0.17] Optical Center of Sensor Array .102 MAX [2.58] 0.281[7.131] Note 319(4X R.0075) [0.19] .560 +.012 -.005 [14.22 + 0.30] [ - 0.12]Notes:1. Controlling dimensions are in inches, values in [] are in millimeters2. All Exposed metallized areas shall be gold plated 60 micro-inches [1.52 micrometers] minimum thickness over nickel plate3. Reference dimensions only. Tolerance will depend on die placement [+/-0.1 mm].4. Reference JEDEC registration MS-009, variation AF issue A, dated 9/29/1980. Confidential36www.national.com

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LM9627 Color CMOS Image Sensor VGA 30 FPSLIFE SUPPORT POLICY

NATIONAL'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORTDEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERALCOUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein:

1.Life support devices or systems are devices or systemswhich, (a) are intended for surgical implant into the body, or(b) support or sustain life, and whose failure to perform whenproperly used in accordance with instructions for use pro-vided in the labeling, can be reasonably expected to result ina significant injury to the user.

National SemiconductorCorporation Americas

Tel: 1-800-272-9959 Fax: 1-800-737-7018

Email: support @ nsc.com

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Email: europe.support @ nsc.comDeutsch Tel: +49 (0) 69 9508 6208English Tel: +44 (0) 870 24 0 2171Francais Tel: +33 (0) 1 41 91 8790

2.A critical component is any component of a life supportdevice or system whose failure to perform can be reasonablyexpected to cause the failure of the life support device orsystem, or to affect its safety or effectiveness.

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Tel: 81-3-5639-7560Fax: 81-3-5639-7507

National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.

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